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Make the Most out of Last Level Cache in Intel Processors
KTH, School of Electrical Engineering and Computer Science (EECS), Communication Systems, CoS, Network Systems Laboratory (NS Lab).ORCID iD: 0000-0001-5083-4052
Ericsson Research.ORCID iD: 0000-0003-4088-7884
KTH, School of Electrical Engineering and Computer Science (EECS), Communication Systems, CoS.ORCID iD: 0000-0002-6066-746X
KTH, School of Electrical Engineering and Computer Science (EECS), Communication Systems, CoS.ORCID iD: 0000-0002-1256-1070
2019 (English)In: Proceedings of the Fourteenth EuroSys Conference (EuroSys'19), Dresden, Germany, 25-28 March 2019., ACM Digital Library, 2019Conference paper, Published paper (Refereed)
Abstract [en]

In modern (Intel) processors, Last Level Cache (LLC) is divided into multiple slices and an undocumented hashing algorithm (aka Complex Addressing) maps different parts of memory address space among these slices to increase the effective memory bandwidth. After a careful study of Intel’s Complex Addressing, we introduce a slice-aware memory management scheme, wherein frequently used data can be accessed faster via the LLC. Using our proposed scheme, we show that a key-value store can potentially improve its average performance ∼12.2% and ∼11.4% for 100% & 95% GET workloads, respectively. Furthermore, we propose CacheDirector, a network I/O solution which extends Direct Data I/O (DDIO) and places the packet’s header in the slice of the LLC that is closest to the relevant processing core. We implemented CacheDirector as an extension to DPDK and evaluated our proposed solution for latency-critical applications in Network Function Virtualization (NFV) systems. Evaluation results show that CacheDirector makes packet processing faster by reducing tail latencies (90-99th percentiles) by up to 119 µs (∼21.5%) for optimized NFV service chains that are running at 100 Gbps. Finally, we analyze the effectiveness of slice-aware memory management to realize cache isolation

Place, publisher, year, edition, pages
ACM Digital Library, 2019.
Keywords [en]
Slice-aware Memory Management, Last Level Cache, Non-Uniform Cache Architecture, CacheDirector, DDIO, DPDK, Network Function Virtualization, Cache Partitioning, Cache Allocation Technology, Key-Value Store.
National Category
Communication Systems
Research subject
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-244750DOI: 10.1145/3302424.3303977ISI: 000470898700008Scopus ID: 2-s2.0-85063919722ISBN: 9781450362818 (print)OAI: oai:DiVA.org:kth-244750DiVA, id: diva2:1291291
Conference
EuroSys'19
Projects
Time-Critical CloudsULTRAWASP
Funder
Wallenberg AI, Autonomous Systems and Software Program (WASP)Swedish Foundation for Strategic Research EU, Horizon 2020, 770889
Note

QC 20190226

Available from: 2019-02-24 Created: 2019-02-24 Last updated: 2019-07-29Bibliographically approved

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fulltext(4195 kB)485 downloads
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Farshin, AlirezaRoozbeh, AmirMaguire Jr., Gerald Q.Kostic, Dejan

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