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Make the Most out of Last Level Cache in Intel Processors
KTH, Skolan för elektroteknik och datavetenskap (EECS), Datavetenskap, Kommunikationssystem, CoS, Network Systems Laboratory (NS Lab).ORCID-id: 0000-0001-5083-4052
Ericsson Research.ORCID-id: 0000-0003-4088-7884
KTH, Skolan för elektroteknik och datavetenskap (EECS), Datavetenskap, Kommunikationssystem, CoS.ORCID-id: 0000-0002-6066-746X
KTH, Skolan för elektroteknik och datavetenskap (EECS), Datavetenskap, Kommunikationssystem, CoS.ORCID-id: 0000-0002-1256-1070
2019 (engelsk)Inngår i: Proceedings of the Fourteenth EuroSys Conference (EuroSys'19), Dresden, Germany, 25-28 March 2019., ACM Digital Library, 2019Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

In modern (Intel) processors, Last Level Cache (LLC) is divided into multiple slices and an undocumented hashing algorithm (aka Complex Addressing) maps different parts of memory address space among these slices to increase the effective memory bandwidth. After a careful study of Intel’s Complex Addressing, we introduce a slice-aware memory management scheme, wherein frequently used data can be accessed faster via the LLC. Using our proposed scheme, we show that a key-value store can potentially improve its average performance ∼12.2% and ∼11.4% for 100% & 95% GET workloads, respectively. Furthermore, we propose CacheDirector, a network I/O solution which extends Direct Data I/O (DDIO) and places the packet’s header in the slice of the LLC that is closest to the relevant processing core. We implemented CacheDirector as an extension to DPDK and evaluated our proposed solution for latency-critical applications in Network Function Virtualization (NFV) systems. Evaluation results show that CacheDirector makes packet processing faster by reducing tail latencies (90-99th percentiles) by up to 119 µs (∼21.5%) for optimized NFV service chains that are running at 100 Gbps. Finally, we analyze the effectiveness of slice-aware memory management to realize cache isolation

sted, utgiver, år, opplag, sider
ACM Digital Library, 2019.
Emneord [en]
Slice-aware Memory Management, Last Level Cache, Non-Uniform Cache Architecture, CacheDirector, DDIO, DPDK, Network Function Virtualization, Cache Partitioning, Cache Allocation Technology, Key-Value Store.
HSV kategori
Forskningsprogram
Datalogi
Identifikatorer
URN: urn:nbn:se:kth:diva-244750DOI: 10.1145/3302424.3303977ISI: 000470898700008Scopus ID: 2-s2.0-85063919722ISBN: 9781450362818 (tryckt)OAI: oai:DiVA.org:kth-244750DiVA, id: diva2:1291291
Konferanse
EuroSys'19
Prosjekter
Time-Critical CloudsULTRAWASP
Forskningsfinansiär
Wallenberg AI, Autonomous Systems and Software Program (WASP)Swedish Foundation for Strategic Research EU, Horizon 2020, 770889
Merknad

QC 20190226

Tilgjengelig fra: 2019-02-24 Laget: 2019-02-24 Sist oppdatert: 2020-05-27bibliografisk kontrollert

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