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Circuit Design Techniques for Implantable Closed-Loop Neural Interfaces
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.ORCID iD: 0000-0002-9862-8255
2019 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Implantable neural interfaces are microelectronic systems, which have the potential to enable a wide range of applications, such as diagnosis and treatment of neurological disorders. These applications depend on neural interfaces to accurately record electrical activity from the surface of the brain, referred to as electrocorticography (ECoG), and provide controlled electrical stimulation as feedback. Since the electrical activity in the brain is caused by ionic currents in neurons, the bridge between living tissue and inorganic electronics is achieved via microelectrode arrays. The conversion of the ionic charge into freely moving electrons creates a built-in electrode potential that is several orders of magnitude larger than the ECoG signal, which increases the dynamic range, resolution, and power consumption requirements of neural interfaces. Also, the small surface area of microelectrodes implies a high-impedance contact, which can attenuate the ECoG signal. Moreover, the applied electrical stimulation can also interfere with the recording and ultimately cause irreversible damages to the electrodes or change their impedance. This thesis is devoted to resolving the challenges of high-resolution recording and monitoring the electrode impedance in implantable neural interfaces.

The first part of this thesis investigates the state-of-the-art neural interfaces for ECoG and identifies their limitations. As a result of the investigation, a high-resolution ADC is proposed and implemented based on a ΔΣ modulator. In order to enhance performance, dynamic biasing and area-efficient switched-capacitor circuits were proposed. The ΔΣ modulator is combined with the analog front-end to provide a complete readout solution for high-resolution ECoG recording. The corresponding chip prototype was fabricated in a 180 nm CMOS process, and the measurement results showed a 14-ENOB over a 300-Hz bandwidth while dissipating 54-μW.

The second part of this thesis expands upon the well-known methods for impedance measurements and proposes an alternative digital method for monitoring the electrode-tissue interface impedance. The proposed method is based on the system identification technique from adaptive digital filtering, and it is compatible with existing circuitry for neural stimulation. The method is simple to implement and performs wide-band measurements. The system identification was first verified through behavioral simulations and then tested with a board-level prototype in order to validate the functionality under real conditions. The measurement results showed successful identification of the electrode-electrolyte and electrode-skin impedance magnitudes.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2019. , p. 72
Series
TRITA-EECS-AVL ; 2019:33
Keywords [en]
Neural interface, ECoG, high-resolution, ADC, recording, delta-sigma modulator, system identification, impedance measurements
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
URN: urn:nbn:se:kth:diva-249435ISBN: 978-91-7873-151-0 (print)OAI: oai:DiVA.org:kth-249435DiVA, id: diva2:1304287
Public defence
2019-05-17, Ka-Sal B (Sal Peter Weissglas), Kistagången 16,, Stockholm, 13:00 (English)
Opponent
Supervisors
Funder
Swedish Research CouncilSwedish Foundation for Strategic Research
Note

QC 20190412

Available from: 2019-04-12 Created: 2019-04-12 Last updated: 2019-04-12Bibliographically approved
List of papers
1. A 96.4 dB High-Pass Delta-Sigma Modulator with Dynamic Biasing and Tree-Structured DEM
Open this publication in new window or tab >>A 96.4 dB High-Pass Delta-Sigma Modulator with Dynamic Biasing and Tree-Structured DEM
2016 (English)In: 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), Vancouver, Canada: IEEE, 2016, article id 7604762Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a switched-capacitor high-pass delta-sigma modulator that can directly convert a chopper modulated signal to the digital domain. Low power consumption is achieved by employing inverter-based amplifiers and dynamic biasing in the first amplifier with relaxed slew-rate requirements as a result of the multi-bit quantization. The mismatch errors in the switched-capacitor DAC are first-order noise shaped by a tree-structured dynamic element matching encoder. Schematic level simulations show that the high-pass modulator achieves a peak SNDR of 96.4 dB and a SFDR of 101 dBc over a bandwidth of 300 Hz. The total estimated power consumption of the modulator is 19.56 mu W leading to a figure-of-merit of 0.6 pJ/conv.

Place, publisher, year, edition, pages
Vancouver, Canada: IEEE, 2016
Series
IEEE International New Circuits and Systems Conference
Keywords
delta-sigma, ADC, modulator, switched-capacitor, DEM, dynamic, element, matching
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-198993 (URN)10.1109/NEWCAS.2016.7604762 (DOI)000386900400028 ()2-s2.0-84999014708 (Scopus ID)978-1-4673-8900-6 (ISBN)
Conference
14th IEEE International New Circuits and Systems Conference (NEWCAS), JUN 26-29, 2016, Vancouver, CANADA
Funder
Swedish Research Council
Note

QC 20170116

Available from: 2017-01-16 Created: 2016-12-22 Last updated: 2019-04-12Bibliographically approved
2. A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems
Open this publication in new window or tab >>A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems
2018 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 05Article in journal (Refereed) Accepted
Abstract [en]

This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-229446 (URN)10.1109/TCSI.2018.2838135 (DOI)000448934700002 ()2-s2.0-85048023102 (Scopus ID)
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-06-04 Created: 2018-06-04 Last updated: 2019-04-12Bibliographically approved
3. Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation
Open this publication in new window or tab >>Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation
2018 (English)Conference paper, Published paper (Refereed)
Abstract [en]

A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is −133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

Place, publisher, year, edition, pages
Florence, Italy: IEEE, 2018
Series
IEEE International Symposium on Circuits and Systems (ISCAS), E-ISSN 2379-447X
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-229449 (URN)10.1109/ISCAS.2018.8351377 (DOI)000451218702062 ()2-s2.0-85057071679 (Scopus ID)978-1-5386-4881-0 (ISBN)978-1-5386-4882-7 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS) 2018
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-06-04 Created: 2018-06-04 Last updated: 2019-05-07Bibliographically approved
4. Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach
Open this publication in new window or tab >>Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach
2017 (English)In: 2017 IEEE Biomedical Circuits and Systems Conference, Turin, October 19-21, 2017, Turin, Italy: Institute of Electrical and Electronics Engineers (IEEE), 2017Conference paper, Published paper (Refereed)
Abstract [en]

Impedance spectroscopy is a low-cost sensing technique that is generating considerable interest in wearable and implantable biomedical applications since it can be efficiently integrated on a single microchip. In this paper, the fundamental characteristics of the most well-known system architectures are presented, and a more robust and hardware-efficient solution is proposed. An all-digital implementation based on adaptive filtering is used for identifying the impedance parameters of a sample-under-test. The coefficients of an infinite-impulse-response (IIR) filter are tuned by an adaptive algorithm based on pseudo-linear regression and output-error formulation. A three-level pseudorandom noise generator with a concave power spectral density is employed without deteriorating the nominal performance. Proof-of-concept has been verified with behavioral simulations.

Place, publisher, year, edition, pages
Turin, Italy: Institute of Electrical and Electronics Engineers (IEEE), 2017
Keywords
Adaptive algorithms, Clocks, Frequency measurement, Impedance, Impedance measurement, Spectroscopy, Systems architecture
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-225867 (URN)10.1109/BIOCAS.2017.8325148 (DOI)2-s2.0-85050013856 (Scopus ID)978-1-5090-5803-7 (ISBN)
Conference
2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017, Politecnico di TorinoTorino, Italy, 19 October 2017 through 21 October 2017
Funder
Swedish Research Council
Note

QC 20180604

Available from: 2018-04-10 Created: 2018-04-10 Last updated: 2019-04-12Bibliographically approved
5. Impedance Spectroscopy Based on Linear System Identification
Open this publication in new window or tab >>Impedance Spectroscopy Based on Linear System Identification
2019 (English)In: IEEE Transactions on Biomedical Circuits and Systems, ISSN 1932-4545, E-ISSN 1940-9990, Vol. 13, no 2, p. 396-402Article in journal (Refereed) Published
Abstract [en]

Impedance spectroscopy is a commonly used mea-surement technique for electrical characterization of a sample-under-test over a wide frequency range. Most measurementmethods employ a sine wave excitation generator, which implies apoint-by-point frequency sweep and a complex readout architec-ture. This paper presents a fast, wide-band, measurement methodfor impedance spectroscopy based on linear system identification.The main advantage of the proposed method is the low hardwarecomplexity, which consists of a 3-level pulse waveform, aninverting voltage amplifier and a general purpose ADC. A proof-of-concept prototype, which is implemented with off-the-shelfcomponents, achieves an estimation fit of approximately 96%.The prototype operation is validated electrically using knownRC component values and tested in real application conditions.

Place, publisher, year, edition, pages
IEEE, 2019
Keywords
Impedance spectroscopy, system identification, adaptive filtering, pseudo-random waveform, IIR filter, ARX.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-244757 (URN)10.1109/TBCAS.2019.2900584 (DOI)000462410800012 ()30794518 (PubMedID)2-s2.0-85061964097 (Scopus ID)
Funder
Swedish Research Council
Note

QC 20190301

Available from: 2019-02-25 Created: 2019-02-25 Last updated: 2019-04-23Bibliographically approved

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Citation style
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Output format
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