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A comparative study of two different schemes to dopant segregation at NiSi/Si and PtSi/Si interfaces for Schottky barrier height lowering
KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
KTH, Skolan för informations- och kommunikationsteknik (ICT).
KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.ORCID-id: 0000-0002-5845-3032
KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
2008 (engelsk)Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, nr 1, s. 396-403Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

An experimental study is presented to compare two different schemes used to incorporate a high concentration of dopants at the silicide/silicon interface for NiSi and PtSi, i.e., dopant segregation, with the purpose of lowering the Schottky barrier height (SBH) of the contact systems. Specifically, the interfacial dopant is introduced either through silicidation-induced dopant segregation (SIDS) or by silicide as diffusion source (SADS). For the latter, a postimplantation drive-in anneal is needed. For both silicide systems, the dopant segregation gives rise to a predominant effect, leading to an effective SBH that is independent of the original SBHs of PtSi and NiSi, which differs by 0.2 eV. Scheme SUDS is relatively simple in processing, but the silicidation process is dopant-dependent, leading to local variations of silicide formation. Scheme SADS addresses the adverse effect of dopant on silicidation by separating silicidation from dopant incorporation.

sted, utgiver, år, opplag, sider
2008. Vol. 55, nr 1, s. 396-403
Emneord [en]
dopant segregation; Schottky barrier (SB) lowering; Schottky diode; silicide
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-7952DOI: 10.1109/TED.2007.911080ISI: 000252059000040Scopus ID: 2-s2.0-37749045251OAI: oai:DiVA.org:kth-7952DiVA, id: diva2:13140
Merknad
QC 20100819Tilgjengelig fra: 2008-02-05 Laget: 2008-02-05 Sist oppdatert: 2018-01-13bibliografisk kontrollert
Inngår i avhandling
1. Integration of silicide nanowires as Schottky barrier source/drain in FinFETs
Åpne denne publikasjonen i ny fane eller vindu >>Integration of silicide nanowires as Schottky barrier source/drain in FinFETs
2008 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. As the device dimensions approach the fundamental limits, novel double/trigate device architecture such as FinFET is needed to guarantee the ultimate downscaling. Furthermore, Schottky barrier source/drain technology presents a promising solution to reducing the parasitic source/drain resistance in the FinFET. The ultimate goal of this thesis is to integrate Schottky barrier source/drain in FinFETs, with an emphasis on process development and integration towards competitive devices.

First, a robust sidewall transfer lithography (STL) technology is developed for mass fabrication of Si-nanowires in a controllable manner. A scalable self-aligned silicide (SALICIDE) process for Pt-silicides is also developed. Directly accessible and uniform NWs of Ni- and Pt-silicides are routinely fabricated by combining STL and SALICIDE. The silicide NWs are characterized by resistivity values comparable to those of their thin–film counterparts.

Second, a systematic experimental study is performed for dopant segregation (DS) at the PtSi/Si and NiSi/Si interfaces in order to modulate the effective SBHs needed for competitive FinFETs. Two complementary schemes SIDS (silicidation induced dopant segregation) and SADS (silicide as diffusion source) are compared, and both yield substantial SBH modifications for both polarities of Schottky diodes (i.e. φbn and φbp).

Third, Schottky barrier source/drain MOSFETs are fabricated in UTB-SOI. With PtSi that is usually used as the Schottky barrier source/drain for p-channel SB-MOSFETs, DS with appropriate dopants leads to excellent performance for both types of SBMOSFETs. However, a large variation in position of the PtSi/Si interface with reference to the gate edge (i.e., underlap) along the gate width is evidenced by TEM.

Finally, integration of PtSi NWs in FinFETs is carried out by combining the STL technology, the Pt-SALICIDE process and the DS technology, all developed during the course of this thesis work. The performance of the p-channel FinFETs is improved by DS with B, confirming the SB-FinFET concept despite device performance fluctuations mostly likely due to the presence of the PtSi-to-gate underlap.

sted, utgiver, år, opplag, sider
Stockholm: KTH, 2008. s. xvi, 80
Serie
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2008:02
Emneord
CMOS technology, MOSFET, FinFET, Schottky diode, Schottky barrier soure/drain, silicide, SALICIDE, SOI, multiple-gate, nanowire, sidewall transfer lithography
HSV kategori
Identifikatorer
urn:nbn:se:kth:diva-4628 (URN)
Disputas
2008-02-19, Sal N1, KTH-Electrum 3, Isafjordsgatan 28, Kista, 10:00
Opponent
Veileder
Merknad
QC 20100923Tilgjengelig fra: 2008-02-05 Laget: 2008-02-05 Sist oppdatert: 2010-09-23bibliografisk kontrollert

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