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Sequential 3D Integration - Design Methodologies and Circuit Techniques
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.ORCID iD: 0000-0002-7534-9317
2019 (English)Doctoral thesis, monograph (Other academic)
Abstract [en]

Sequential 3D (S3D) integration has been identified as a potential candidate for area efficient ICs. It entails the sequential processing of tiers of devices, one on top the other. The sequential nature of this processing allows the inter-tier vias to be processed like any other inter-metal vias, resulting in an unprecedented increase in the density of vertical interconnects. A lot of scientific attention has been directed towards the processing aspects of this 3-D integration approach, and in particular producing high-performance top-tier transistors without damaging the bottom tier devices and interconnects.As far as the applications of S3D integration are concerned, a lot of focus has been placed on digital circuits. However, the advent of Internet-of-Things applications has motivated the investigation of other circuits as well.

As a first step, two S3D design platforms for custom ICs have been developed, one to facilitate the development of the in-house S3D process and the other to enable the exploration of S3D applications. Both contain device models and physical verification scripts. A novel parasitic extraction flow for S3D ICs has been also developed for the study of tier-to-tier parasitic coupling.

The potential of S3D RF/AMS circuits has been explored and identified using these design platforms. A frequency-based partition scheme has been proposed, with high frequency blocks placed in the top-tier and low-frequency ones in the bottom. As a proof of concept, a receiver front-end for the ZigBee standard has been designed and a 35% area reduction with no performance trade-offs has been demonstrated.

To highlight the prospects of S3D RF/AMS circuits, a study of S3D inductors has been carried out. Planar coils have been identified as the most optimal configuration for S3D inductors and ways to improve their quality factors have been explored. Furthermore, a set of guidelines has been proposed to allow the placement of bottom tier blocks under top-tier inductors towards very compact S3D integration. These guidelines take into consideration the operating frequencies and type of components placed in the bottom tier.

Lastly, the prospects of S3D heterogeneous integration for circuit design have been analyzed with the focus lying on a Ge-over-Si approach. Based on the results of this analysis, track-and-hold circuits and digital cells have been identified as potential circuits that could benefit the most from a Ge-over-Si S3D integration scheme, thanks to the low on-resistance of Ge transistors in the triode region. To improve the performance of top-tier Ge transistors, a processing flow that enables the control of their back-gates has been also proposed, which allows controlling the threshold voltage of top-tier transistors a truntime.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2019. , p. iii-xxi, 138
Series
TRITA-EECS-AVL ; 2019:54
Keywords [en]
sequential 3D integration, monolithic inter-tier vias, design platforms, parasitic extraction flows, RF/AMS circuits, inductors, heterogeneous integration, germanium transistors
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
URN: urn:nbn:se:kth:diva-252127ISBN: 978-91-7873-228-9 (print)OAI: oai:DiVA.org:kth-252127DiVA, id: diva2:1317812
Public defence
2019-08-30, Sal C, Kungl Tekniska högskolan, Kistagången 16, Kista, Stockholm, 13:00 (English)
Opponent
Supervisors
Funder
Swedish Foundation for Strategic Research
Note

QC 20190524

Available from: 2019-05-24 Created: 2019-05-24 Last updated: 2019-06-10Bibliographically approved

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12345673 of 11
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Citation style
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