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Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing
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2014 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 63, no 3, p. 718-733Article in journal (Refereed) Published
Abstract [en]

Combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain in ChipMultiprocessors (CMPs) architectures. As multicast communication is commonly used in cache coherence protocols for CMPs and invarious parallel applications, the performance of these systems can be significantly improved if multicast operations are supported at thehardware level. In this paper, we present several partitioning methods for the path-based multicast approach in 3D mesh-based NoCs,each with different levels of efficiency. In addition, we develop novel analytical models for unicast and multicast traffic to explore theefficiency of each approach. In order to distribute the unicast and multicast traffic more efficiently over the network, we propose theMinimal and Adaptive Routing (MAR) algorithm for the presented partitioning methods. The analytical and experimental results show thatan advantageous method named Recursive Partitioning (RP) outperforms the other approaches. RP recursively partitions the networkuntil all partitions contain a comparable number of switches and thus the multicast traffic is equally distributed among several subsetsand the network latency is considerably decreased. The simulation results reveal that the RP method can achieve performanceimprovement across all workloads while performance can be further improved by utilizing the MAR algorithm. Nineteen percent averageand 42 percent maximum latency reduction are obtained on SPLASH-2 and PARSEC benchmarks running on a 64-core CMP.

Place, publisher, year, edition, pages
2014. Vol. 63, no 3, p. 718-733
Keywords [en]
cache storage;multicast communication;multiprocessing systems;network routing;network-on-chip;parallel processing;switching networks;three-dimensional integrated circuits;path-based partitioning method;3D networks-on-chip;minimal adaptive routing;3D IC;chip multiprocessors;CMP architecture;multicast communication;cache coherence protocol;parallel application;hardware level multicast operation support;path-based multicast approach;3D mesh-based NoC;unicast traffic;multicast traffic;MAR algorithm;recursive partitioning;switch;network latency;performance improvement;latency reduction;SPLASH-2 benchmark;PARSEC benchmark;Unicast;Routing;Partitioning algorithms;Protocols;Multicast communication;Algorithm design and analysis;System recovery;3D Networks-on-Chip;unicast and multicast communication;partitioning methods;analytical models;adaptive routing algorithm
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Other Electrical Engineering, Electronic Engineering, Information Engineering Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-254865DOI: 10.1109/TC.2012.255OAI: oai:DiVA.org:kth-254865DiVA, id: diva2:1335733
Note

QC 20190819

Available from: 2019-07-07 Created: 2019-07-07 Last updated: 2019-08-19Bibliographically approved

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Ebrahimi, MasoumehTenhunen, Hannu

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