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Applications of Si1-xGex alloys for Ge devices and monolithic 3D integration
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0003-0568-0984
2020 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

As the semiconductor industry moves beyond the 10 nm node, power consumption constraints and reduction of the negative impact of parasitic elements become important. Silicon germanium (Si1−xGex) alloys have been used to amplify the performance of Si based devices and integrated circuits (ICs) for decades. Selective epitaxial growth of heavily doped Si and/or Si1−xGex is commonly employed to reduce the effect of parasitic resistance. Reducing the supply voltage leads to lower dynamic power consumption in complementary metal-oxide-semiconductor (CMOS) technology. Monolithic three-dimensional integration (M3D) is a technology that employs vertical stacking of the device tiers. This approach reduces the wiring length, effectively reducing interconnect delay, load capacitance and ultimately reducing the power consumption. Among the integration challenges M3D is facing, one can distinguish the available thermal budget for fabrication, the crystalline quality of the device active layer and finally the actual device or circuit performance.Germanium channel devices can benefit M3D integration. Germanium metal-oxide-semiconductor field-effect transistors (MOSFETs) can be fabricated at significantly lower temperatures than Si. In addition, they potentially can have higher performance compared to Si due to the superior electron and hole mobilities of Ge. Active layer transfer of crystalline quality layers is a key step in a M3D fabrication flow. Direct wafer bonding techniques offerthe possibility to transfer a Ge layer on a patterned wafer. This thesis studies the various applications of Si1−xGex films in M3D. An initial implementation of an in situ doped Si1−xGex film on silicon-on-insulator (SOI) and germanium substrates is first presented. A Si1−xGex film isgrown selectively on SOI substrates to be used as a contact electrode on Si nanowire biosensors. On Ge bulk substrates, in situdoped Si1−xGex is epitaxially grown to form p+-n junctions. The junction leakage current and the mechanisms at play are studied. The analysis ofthe junction performance provides insights on the junction leakage mechanisms,an important issue for the implementation of in situ doped Si1−xGex in M3D. A low temperature germanium-on-insulator (GOI) fabrication flow based on room temperature wafer bonding and etch back is presented in this work. The method suggested in the thesis produces high quality, crystalline Ge device layers with excellent uniformity. The thesis also reports on the development and integration of Si1−xGex in the GOI fabrication as an etch stop layer, enabling the stability of the layer transfer process. Finally this thesis presents Ge p-channel field-effect transistor (PFET) devices fabricated on the previously developed GOI substrates.The technologies presented in this thesis can be integrated in large scale Ge device fabrication. The low temperature GOI and Ge PFET fabrication methods are very well suited for sequential device fabrication. The processes and applications presented in this thesis meet the current thermal budget, device performance and active layer transfer demands for M3D technology.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2020. , p. 87
Series
TRITA-EECS-AVL ; 2020:5
Keywords [en]
Silicon, germanium, epitaxy, selective, pn junction, germanium on insulator, GOI, Ge PFET, bonding, monolithic, sequential, three dimensional, 3D, low temperature
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
URN: urn:nbn:se:kth:diva-269412ISBN: 978-91-7873-465-8 (print)OAI: oai:DiVA.org:kth-269412DiVA, id: diva2:1412480
Public defence
2020-04-03, Join Zoom Meeting https://kth-se.zoom.us/j/664249709, 13:00 (English)
Opponent
Supervisors
Funder
Swedish Foundation for Strategic Research , 66197
Note

QC 20200310

Disputation via Zoom (Campus closed)

Join Zoom Meeting

https://kth-se.zoom.us/j/664249709

Available from: 2020-03-10 Created: 2020-03-06 Last updated: 2020-03-30Bibliographically approved
List of papers
1. Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density
Open this publication in new window or tab >>Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density
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2016 (English)In: ECS Transactions, Electrochemical Society, 2016, no 8, p. 615-621Conference paper, Published paper (Refereed)
Abstract [en]

Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

Place, publisher, year, edition, pages
Electrochemical Society, 2016
Keywords
Chemical vapor deposition, Silicon, Silicon alloys, Strain relaxation, Surface defects, Surface roughness, Surface topography, Temperature, Defects density, Low-dislocation density, Low-temperature grown, Mobility enhancement, Reduced pressure chemical vapor deposition, Strain relaxed buffers, Strain-relaxed, Threading dislocation densities, Germanium
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-201995 (URN)10.1149/07508.0615ecst (DOI)2-s2.0-84991585471 (Scopus ID)9781607685395 (ISBN)
Conference
Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016
Note

QC 20170224

Available from: 2017-02-24 Created: 2017-02-24 Last updated: 2020-03-06Bibliographically approved
2. Germanium on Insulator Fabrication for Monolithic 3-D Integration
Open this publication in new window or tab >>Germanium on Insulator Fabrication for Monolithic 3-D Integration
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2018 (English)In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed) Published
Abstract [en]

A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018
Keywords
GOI, wafer bonding, selective etching, GOI MOSFET, 3D integration
National Category
Materials Chemistry
Identifiers
urn:nbn:se:kth:diva-231645 (URN)10.1109/JEDS.2018.2801335 (DOI)000435505000007 ()2-s2.0-85041650674 (Scopus ID)
Funder
Swedish Foundation for Strategic Research
Note

QC 20180904

Available from: 2018-09-04 Created: 2018-09-04 Last updated: 2020-03-06Bibliographically approved
3. Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration
Open this publication in new window or tab >>Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration
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2015 (English)In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015, p. 165-168Conference paper, Published paper (Refereed)
Abstract [en]

We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C-350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.

Keywords
3D integration, atomic layer deposition, current leakage, defects, Ge, GeOI, inter layer dielectrics, monolithic, strained Ge, wafer bonding, Deposition, Germanium, Integration, Leakage (fluid), Monolithic integrated circuits, Silicon wafers, Surface roughness, Three dimensional integrated circuits, 3-D integration, Inter-layer dielectrics, Strained-Ge
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-167390 (URN)10.1109/ULIS.2015.7063799 (DOI)000380427400042 ()2-s2.0-84926444085 (Scopus ID)9781479969111 (ISBN)
External cooperation:
Conference
2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015; Bologna; Italy; 26 January 2015 through 28 January 2015
Note

QC 20150529

Available from: 2015-05-29 Created: 2015-05-22 Last updated: 2020-03-06Bibliographically approved
4. Silicon nanowires integrated with CMOS circuits for biosensing application
Open this publication in new window or tab >>Silicon nanowires integrated with CMOS circuits for biosensing application
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2014 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 98, p. 26-31Article in journal (Refereed) Published
Abstract [en]

We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N-2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

Keywords
Nanowire, Biosensing, SOI, CMOS, STL
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-149200 (URN)10.1016/j.sse.2014.04.005 (DOI)000339149000006 ()2-s2.0-84902251547 (Scopus ID)
Funder
EU, European Research Council, 228229
Note

QC 20140818

Available from: 2014-08-18 Created: 2014-08-18 Last updated: 2020-03-06Bibliographically approved
5. Fabrication and characterization of silicon nanowires using STL for biosensing applications
Open this publication in new window or tab >>Fabrication and characterization of silicon nanowires using STL for biosensing applications
2014 (English)In: INT CONF ULTI INTEGR, ISSN 2330-5738, p. 109-112Article in journal (Refereed) Published
Abstract [en]

We present a sidewall transfer lithography (STL) process to fabricate silicon nanowires using the CMOS compatible materials SiO2, SiN and alpha-Si. The STL process is implemented using a single cluster tool for reactive ion etching (RIE) and plasma enhanced chemical vapor deposition (PECVD) with a maximum process temperature of 400 degrees C. Using three lithography masks, single and multiple silicon nanowires connected to contact areas can be defined. By optimizing layer thicknesses, RIE and deposition conformity we demonstrate wafer scale definition of 60 nm wide silicon nanowires using I-line stepper lithography. The silicon nanowires exhibit excellent characteristics for biosensing applications with subthreshold slopes of 75 mV/dec and a high on/off current ratio of more than 10(5).

Keywords
nanowire, biosensing, SOI, CMOS, STL, step coverage, threshold voltage, subthreshold slope
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-153866 (URN)10.1109/ULIS.2014.6813928 (DOI)000341731300028 ()2-s2.0-84901357181 (Scopus ID)
Conference
15th International Conference on Ultimate Integration on Silicon (ULIS), APR 07-09, 2014, Stockholm, SWEDEN
Note

QC 20141009

Available from: 2014-10-09 Created: 2014-10-09 Last updated: 2020-03-06Bibliographically approved

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