True Random Number Generators (TRNGs) and Physical Unclonable Functions (PUFs) are two important types of cryptographic primitives. TRNGs create a hardware-based, non-deterministic noise that is often used for generating keys, initialization vectors, and nonces for various applications that require cryptographic protection. PUFs have been proposed as a tamper-resistant alternative to the traditional secret key generation and challenge-response authentication methods. A compromised TRNG or PUF can lead to a system-wide loss of security.

The conventional TRNG or PUF designs are challenged by new attack vectors such as deep learning-based side-channel analysis. In this dissertation, we propose several new PUF and TRNG designs and evaluations of their performance and security.

The first PUF we introduce is called threshold PUF. We show that, in principle, any n-input threshold logic gate can be used as a base for building an n-input PUF. We implement and evaluate a threshold PUF based on recently proposed threshold logic flip-flops using SPICE simulation as a proof of concept. Threshold PUFs open up the possibility of using the rich body of knowledge on threshold logic implementations for designing PUFs. 

The second proposed design is a lightweight PUF construction called CRC-PUF, which focuses on protecting PUFs against machine learning-based modeling attacks. In CRC-PUF, input challenges are de-synchronized from output responses to make the PUF model difficult to learn. The input transformation which does the de-synchronization is based on a Cyclic Redundancy Check (CRC), thus the name CRC-PUF. By changing the CRC generator polynomial for each new response, we assure that recovering the transforming challenge has a success probability of at most 2^-86 for 128-bit challenge-response pairs.

The first TRNG design we introduce is based on a Non-Linear Feedback Ring Oscillator (NLFRO). The proposed NLFRO-TRNG structure harvests randomness from noise and unpredictable variations in delay cells and bi-stable elements, which is further amplified by the formation of non-linear feedback loops. The NLFRO outputs have chaotic behavior, allowing the construction of TRNGs with high entropy and speed. We implement three NLFRO-TRNGs on FPGA and evaluate the properties of the implementations with the NIST 800-90B entropy estimation and NIST 800-22 statistical test suits. 

The second proposed TRNG design is based on a strong PUF. The PUF based TRNG exploits the inherent determinism of PUF to enable in-field testing of the entropy sources by known answer tests. We present a prototype FPGA implementation of the proposed TRNG based on an arbiter PUF that passes all NIST 800-22 statistical tests and has the minimal entropy of 0.918 estimated according to NIST 800-90B recommendations.

Apart from TRNG and PUF designs, it is crucial to consider potential attack vectors that can be created leveraging recently emerged technologies. To that end, in the second part of this dissertation, we introduce a novel attack on FPGA-based PUF and TRNG implementations that combines bitstream modification along with deep learning-based side-channel analysis. We evaluate this new attack vector on the design of an arbiter PUF and a ring oscillator-based TRNG implemented on Xilinx Artix-7 28nm FPGAs. In both cases, we are able to achieve close to 100% classification accuracy to recover the output or response. In the case of the arbiter PUF, the attack can even overcome countermeasures that are based on encrypting the challenges or responses.

With such potent attack vectors readily available, the construction of strong countermeasures is necessary. Unfortunately, many of the state-of-the-art countermeasures are one-sided. In the final part of the dissertation, we use a countermeasure proposed for the protection of the Advanced Encryption Standard as an example. We conduct experiments and conclude that it can assist another type of side-channel attack that is not considered by the countermeasure.

Field-programmable gate arrays (FPGAs) are used across various industries due to their high performance, energy efficiency, and reconfigurability. However, the major advantage of reconfigurability is also a source of security challenges.The present doctoral thesis investigates the security vulnerabilities of the FPGA configuration file, i.e. the bitstream, focusing on the exploration and mitigation of targeted bitstream modification attacks. The results outlined in the seven chapters of the thesis are based on the appended collection of twelve papers. Out of those papers, seven present novel research on the topic of bitstream modification attacks and countermeasures, with the majority of contributions being on attacks. Four present novel research on the topic of FPGA-based countermeasures against side-channel analysis. The final paper presents a survey on bitstream modification attacks and countermeasures. The motivation behind the papers on side-channel countermeasures is to enhance the FPGA encryption schemes, as strong encryption can thwart targeted bitstream modification attacks. 

The attack vector of targeted bitstream modification is explored through a series of attacks against cryptographic FPGA implementations. The targets are popular stream ciphers (SNOW 3G, ACORN, and Trivium) and cryptographic primitives (an arbiter-based physical unclonable function and multi-ring-oscillator-based true random number generator). In the attacks on stream ciphers, the bitstream is modified to introduce faults that weaken the keystream by linearizing its generation process. A subsequent analysis of that faulty keystream reveals the secret key of the implementations. In the attacks on cryptographic primitives, the goal of the bitstream modification attack is to lower the bar or enable a side-channel analysis. The aim of the side-channel analysis is to predict the random output values produced by the primitives. To facilitate that, the bitstream modification attack identifies components in the bitstream that produce exploitable information leakage and creates multiple copies of them. The copies have the same values as the targets, but their outputs are not connected, thus having no impact on the functionality of the design. The study on bitstream modification is complemented with the introduction of low-cost obfuscation countermeasures and a general-purpose methodology against obfuscation based on constants. The methodology is able to defeat all the countermeasures we have previously defined, and its application extends to the general field of hardware design obfuscation.

On the topic of side-channel analysis countermeasures, the popular methodology of clock randomization is evaluated. The assumed side-channel analysis aims to extract the secret key of the advanced encryption standard (AES) block cipher. The evaluation reveales that clock randomization cannot offer protection when the side-channel measurements are sampled at a frequency significantly higher than the operational frequency of the device. In response to that, the clock randomization technique is coupled with encryption core duplication to form, a novel countermeasure called CRCD (clock randomization with encryption core duplication). The countermeasure is shown to effectively protect implementations of block ciphers such as AES, and post-quantum key encapsulation mechanisms such as CRYSTALS-Kyber. Further analysis of the countermeasure reveals a weakness that is exploited and finally patched in an updated implementation of CRCD.

Field-Programmable Gate Arrays (FPGAer) används inom olika branscher på grund av deras höga prestanda, energieffektivitet och omkonfigurerbarhet. Dock är den stora fördelen med omkonfigurerbarhet också en källa till säkerhetsutmaningar.Denna doktorsavhandling undersöker säkerhetsbristerna i FPGA-konfigurationsfilen, d.v.s. bitströmmen, med fokus på utforskning och mildring av riktade bitströmsmodifieringsattacker. Resultaten som redogörs i avhandlingens sju kapitel baseras på en bilagd samling av tolv artiklar. Av dessa artiklar presenterar sju ny forskning om ämnet bitströmsmodifieringsattacker och motåtgärder, med majoriteten av bidragen om attacker. Fyra presenterar ny forskning om ämnet FPGA-baserade motåtgärder mot sidokanalsanalys. Den sista rapporten presenterar en översikt över bitströmsmodifieringsattacker och motåtgärder. Motivationen för rapporterna om sidokanalmotåtgärder är att förbättra FPGA-krypteringsscheman, eftersom stark kryptering kan förhindra riktade bitströmsmodifieringsattacker.

Attackvektorn för riktade bitströmsmodifieringsattacker utforskas genom en serie attacker mot kryptografiska FPGA-implementationer. Målen är populära flödes-chiffer (SNOW 3G, ACORN och Trivium) och kryptografiska primitiv (en arbiter-baserad fysiskt oklonbar funktion och en multi-ring-oscillator-baserad sann slumpmässig nummergenerator). I attackerna på strömkrypteringar modifieras bitströmmen för att introducera fel som försvagar keystreamen genom att linjärisera dess genereringsprocess. En efterföljande analys av den felaktiga keystreamen avslöjar den hemliga nyckeln för implementationerna. I attackerna på kryptografiska primitiv är målet med bitströmsmodi-\\fieringsattacken att sänka ribban eller möjliggöra en sidokanalsanalys. Målet med sidokanalsanalysen är att förutsäga de slumpmässiga utvärdena som produceras av primitiverna. För att underlätta detta identifierar bitströmsmodifieringsattacken komponenter i bitströmmen som producerar utnyttjbar informationsläckage och skapar fler kopior av dem. Kopiorna har samma värden som målen, men deras utgångar är inte anslutna, vilket inte påverkar designens funktionalitet. Studien om bitströmsmodifiering kompletteras med införandet av lågkostnadsförvirringsmotåtgärder och en allmän metodik mot förvirring baserad på konstanter. Metodiken kan besegra alla de motåtgärder vi tidigare definierat, och dess tillämpning sträcker sig till det allmänna området för hårdvarudesignförvirring.

På ämnet motåtgärder mot sidokanalsanalys utvärderas den populära metoden för klockslumpning. Den antagna sidokanalsanalysen syftar till att extrahera den hemliga nyckeln för blockkryptoalgoritmen advanced encryption standard (AES). Utvärderingen visar att klockslumpning inte kan erbjuda skydd när sidokanalsmätningarna samplas med en frekvens som är avsevärt högre än enhetens driftfrekvens. Som svar på detta kombineras tekniken för klockslumpning med duplication av krypteringskärnan för att bilda en ny motåtgärd som kallas CRCD (clock randomization with encryption core duplication). Motåtgärden har visat sig effektivt skydda implementationer av blockkrypteringar som AES och postkvantum nyckelinkapslingsmekanismer som CRYSTALS-Kyber. Ytterligare analys av motåtgärden avslöjar en svaghet som utnyttjas och slutligen åtgärdas i en uppdaterad implementation av CRCD.