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Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design
KTH, School of Electrical Engineering and Computer Science (EECS).ORCID iD: 0000-0002-7693-6994
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0002-5697-4272
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.ORCID iD: 0000-0003-0565-9376
2021 (English)In: Proceedings - 2021 15th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2021, Association for Computing Machinery (ACM), 2021, p. 61-66Conference paper, Published paper (Refereed)
Abstract [en]

Synchoros VLSI design style has been proposed as an alternative to the standard cell-based design style; the word synchoros is derived from the Greek word choros for space. Synchoricity discretises space with a virtual grid, the way synchronicity discretises time with clock ticks. SiLago (Silicon Lego) blocks are atomic synchoros building blocks like Lego bricks. SiLago blocks absorb all metal layer details, i.e., all wires, to enable composition by abutment of valid; valid in the sense of being technology design rules compliant, timing clean and OCV ruggedized. Effectively, composition by abutment eliminates logic and physical synthesis for the end user. Like Lego system, synchoricity does need a finite number of SiLago block types to cater to different types of designs. Global NoCs are important system level design components. In this paper, we show, how with a small library of SiLago blocks for global NoCs, it is possible to automatically synthesize arbitrary global NoCs of different types, dimensions, and topology. The synthesized global NoCs are not only valid VLSI designs, but their cost metrics (area, latency, and energy) are known with post-layout accuracy in linear time. We argue that this is essential to be able to do chip-level design space exploration. We show how the abstract timing model of such global NoC SiLago blocks can be built and used to analyse the timing of global NoC links with post layout accuracy and in linear time. We validate this claim by subjecting the same VLSI designs of global NoC to commercial EDA's static timing analysis and show that the abstract timing analysis enabled by synchoros VLSI design gives the same results as the commercial EDA tools.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2021. p. 61-66
Series
International Symposium on Networks-on-Chip, ISSN 2474-3739
Keywords [en]
Coarse Grain Reconfigurable Architectures, Clock Tree Synthesis, VLSI design, SiLago
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-310025DOI: 10.1145/3479876.3481594ISI: 000758600000010Scopus ID: 2-s2.0-85118159662OAI: oai:DiVA.org:kth-310025DiVA, id: diva2:1646572
Conference
NOCS '21: International Symposium on Networks-on-Chip Virtual Event October 14 - 15, 2021
Note

QC 20220323

Part of proceedings: ISBN 978-1-4503-9083-5

Available from: 2022-03-23 Created: 2022-03-23 Last updated: 2022-06-25Bibliographically approved

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Altayo Gonzalez, u1dr0yqpStathis, DimitriosHemani, Ahmed

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School of Electrical Engineering and Computer Science (EECS)Electronics and Embedded systemsElectronic and embedded systems
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CiteExportLink to record
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