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Assessing the State of Autovectorization Support based on SVE
Forschungszentrum Julich, Julich Supercomp Ctr, Julich, Germany..
KTH, Skolan för elektroteknik och datavetenskap (EECS), Centra, Parallelldatorcentrum, PDC.ORCID-id: 0000-0001-7296-7817
2022 (engelsk)Inngår i: 2022 IEEE INTERNATIONAL CONFERENCE ON CLUSTER COMPUTING (CLUSTER 2022), Institute of Electrical and Electronics Engineers (IEEE) , 2022, s. 556-562Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

So-called SIMD instructions, which trigger operations that process in each clock cycle a data tuple, have become widespread in modern processor architectures. In particular, processors for high-performance computing (HPC) systems rely on this additional level of parallelism to reach a high throughput of arithmetic operations. Leveraging these SIMD instructions can still be challenging for application software developers. This challenge has become simpler due to a compiler technique called auto-vectorization. In this paper, we explore the current state of auto-vectorization capabilities using state-of-the-art compilers using a recent extension of the Arm instruction set architecture, called SVE. We measure the performance gains on a recent processor architecture supporting SVE, namely the Fujitsu A64FX processor.

sted, utgiver, år, opplag, sider
Institute of Electrical and Electronics Engineers (IEEE) , 2022. s. 556-562
Serie
IEEE International Conference on Cluster Computing, ISSN 1552-5244
Emneord [en]
ISA, auto-vectorization, Arm, SVE
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-324314DOI: 10.1109/CLUSTER51413.2022.00073ISI: 000920273100058Scopus ID: 2-s2.0-85140893554OAI: oai:DiVA.org:kth-324314DiVA, id: diva2:1739621
Konferanse
IEEE International Conference on Cluster Computing (CLUSTER), SEP 06-09, 2022, Heidelberg, GERMANY
Merknad

Part of proceedings: ISBN 978-1-6654-9856-2QC 20230227

Tilgjengelig fra: 2023-02-27 Laget: 2023-02-27 Sist oppdatert: 2023-02-27bibliografisk kontrollert

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