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COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores
Jülich Supercomputing Centre, Novel System Architectures Design, Forschungszentrum Jülich GmbH, Jülich, Germany.
Jülich Supercomputing Centre, Novel System Architectures Design, Forschungszentrum Jülich GmbH, Jülich, Germany.
Jülich Supercomputing Centre, Novel System Architectures Design, Forschungszentrum Jülich GmbH, Jülich, Germany.
Institute of Computer Science, Foundation for Research and Technology - Hellas (FORTH), Heraklion, Greece.
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2023 (Engelska)Ingår i: Architecture of Computing Systems: 36th International Conference, ARCS 2023, Proceedings, Springer Nature , 2023, s. 105-119Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

This paper explores the memory subsystem design through gem5 simulations of a non-uniform memory access (NUMA) architecture with ARM cores equipped with vector engines. And connected to a Network-on-Chip (NoC) following the Coherent Hub Interface (CHI) protocol. The study quantifies the benefits of vectorization, prefetching, and multichannel NoC configurations using a benchmark for generating memory patterns and indexed accesses. The outcomes provide insights into improving bus utilization and bandwidth and reducing stalls in the system. The paper proposes hardware/software (HW/SW) advancements to reach and use the HBM device with a higher percentage than 80% at the memory controllers in the simulated manycore system.

Ort, förlag, år, upplaga, sidor
Springer Nature , 2023. s. 105-119
Nyckelord [en]
Co-design, gem5, HPC, Network on Chip
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URN: urn:nbn:se:kth:diva-337883DOI: 10.1007/978-3-031-42785-5_8Scopus ID: 2-s2.0-85171444909OAI: oai:DiVA.org:kth-337883DiVA, id: diva2:1803851
Konferens
36th International Conference on Architecture of Computing Systems, ARCS 2023, Athens, Greece, Jun 13 2023 - Jun 15 2023
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Part of ISBN 9783031427848

QC 20231010

Tillgänglig från: 2023-10-10 Skapad: 2023-10-10 Senast uppdaterad: 2023-10-10Bibliografiskt granskad

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Pleiter, Dirk

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