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CPU Architecture Modelling and Co-design
Microsoft, Munich, Germany.
KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Computational Science and Technology (CST).ORCID iD: 0000-0001-7296-7817
2023 (English)In: High Performance Computing - 38th International Conference, ISC High Performance 2023, Proceedings, Springer Nature , 2023, p. 3-21Conference paper, Published paper (Refereed)
Abstract [en]

Co-design has become an established process for both developing high-performance computing (HPC) architectures (and, more specifically, CPU architectures) as well as HPC applications. The co-design process is frequently based on models. This paper discusses an approach to CPU architecture modelling and its relation to modelling theory. The approach is implemented using the gem5 simulator for Arm-based CPU architectures and applied for the purpose of generating co-design knowledge using two applications that are widely used on HPC systems.

Place, publisher, year, edition, pages
Springer Nature , 2023. p. 3-21
Keywords [en]
Arm, computer architecture modelling, computer architecture simulation, gem5, GPAW, Graviton 2, GROMACS, HPC applications, HPC architectures
National Category
Computer Sciences Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-338629DOI: 10.1007/978-3-031-32041-5_1Scopus ID: 2-s2.0-85161134699OAI: oai:DiVA.org:kth-338629DiVA, id: diva2:1809156
Conference
38th International Conference on High Performance Computing, ISC High Performance 2023, Hamburg, Germany, May 21 2023 - May 25 2023
Note

Part of ISBN 9783031320408

QC 20231102

Available from: 2023-11-02 Created: 2023-11-02 Last updated: 2023-11-02Bibliographically approved

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Pleiter, Dirk

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