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Minimal-power, delay-balanced SMART repeaters for global interconnects in the nanometer regime
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0001-9588-0239
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-1959-6513
2008 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 16, no 5, p. 589-593Article in journal (Refereed) Published
Abstract [en]

A SMART repeater is proposed for driving capacitively-coupled, global-length on-chip interconnects that alters its drive strength dynamically to match the relative bit pattern on the wires and thus the effective capacitive load. This is achieved by partitioning the driver into main and assistant drivers; for a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. In a UMC 0.18-mu m technology the potential energy saving is around 10% and the reduction in jitter 20%, in comparison to a traditional repeater for typical global wire lengths. It is also shown that the average energy saving for nanometer technologies is in the range of 20% to 25%. The driver architecture exploits the fact that as feature sizes decrease, the capacitive load per transistor shrinks, whereas global wire loads remain relatively unchanged. Hence, the smaller the technology, the greater the potential saving.

Place, publisher, year, edition, pages
2008. Vol. 16, no 5, p. 589-593
Keywords [en]
buffer, interconnects, nanometer design, on-chip signaling, repeaters
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-17783DOI: 10.1109/tvlsi.2008.917555ISI: 000258762700009Scopus ID: 2-s2.0-42649123682OAI: oai:DiVA.org:kth-17783DiVA, id: diva2:335828
Note
QC 20100525Available from: 2010-08-05 Created: 2010-08-05 Last updated: 2024-01-08Bibliographically approved

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Zheng, Li-RongTenhunen, Hannu
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VinnExcellence Center for Intelligence in Paper and Packaging, iPACKElectronic, Computer and Software Systems, ECS
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IEEE Transactions on Very Large Scale Integration (vlsi) Systems
Electrical Engineering, Electronic Engineering, Information Engineering

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