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Examination of Delay and Signal Integrity Metrics in Through Silicon Vias
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
2009 (engelsk)Inngår i: DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test, Electronic Workshop Digest, Palais des Congrès Acropolis – Nice, France, Friday April 24, 2009, Nice, France, 2009, s. 260-264Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

This article discusses results from simulations of signaling in Through Silicon Vias (TSVs) with an emphasis on latency and signal integrity effects. Data from field solver simulations is used for TSV parasitics and employed in SPICE simulations. A reduced order electrical circuit is proposed for lone TSVs as well as bundled structures and switch-factor based delay models are derived to calculate rise times in a 3x3 bundle. Furthermore Signal Integrity (SI) issues in coupled TSVs are briefly discussed.

sted, utgiver, år, opplag, sider
Nice, France, 2009. s. 260-264
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-79240OAI: oai:DiVA.org:kth-79240DiVA, id: diva2:495281
Konferanse
DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test, Nice, France, April 24, 2009
Prosjekter
EU-FP7 ELITE-215030
Merknad
QC 20120209Tilgjengelig fra: 2012-02-08 Laget: 2012-02-08 Sist oppdatert: 2012-02-10bibliografisk kontrollert

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http://www.date-conference.com/files/file/09-workshops/date09-3dws-digestv2-090504.pdf

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