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Asynchronous BFT for low power networks on chip
KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar. Ohio State University, Columbus, OH, United States . (RaMSiS Group)
2010 (engelsk)Inngår i: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, IEEE , 2010, s. 3240-3243Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Asynchronous Butterfly Fat Tree (BFT) architecture is proposed to achieve low power Network on Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches (αdata satisfies a certain condition. The area of Asynchronous BFT switch is increased by 25% as compared to Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by up to 33% as compared to the power dissipation of the conventional Synchronous architecture when the αdata equals 0.2 and the activity factor of the control signals is equal to 1/64 of the αdata. The total metal resources required to implement Asynchronous design is decreased by 12%.

sted, utgiver, år, opplag, sider
IEEE , 2010. s. 3240-3243
Serie
IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
Emneord [en]
BFT, GALS, Low power, NoC
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-149605DOI: 10.1109/ISCAS.2010.5537922ISI: 000287216003114Scopus ID: 2-s2.0-77956006799ISBN: 978-1-4244-5309-2 (tryckt)OAI: oai:DiVA.org:kth-149605DiVA, id: diva2:740451
Konferanse
2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, 30 May 2010 through 2 June 2010, Paris, France
Merknad

QC 20140825

Tilgjengelig fra: 2014-08-25 Laget: 2014-08-25 Sist oppdatert: 2014-08-25bibliografisk kontrollert

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