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Power efficient networks on chip
KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
2009 (engelsk)Inngår i: 2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, 2009, s. 105-108Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduce. The power consumption oy the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover. The power reduction technique is applied to different NoC architectures. The technique reduce. The power consumption oy the network by up to 41%. Whe. The power consumption oy the whole network includin. The interswich links and repeaters is taken into account. The overall power consumption is decreased by up to 33% at the maximum operating frequency oy the switch. The BFT architecture consume. The minimum power as compared to other NoC architectures.

sted, utgiver, år, opplag, sider
2009. s. 105-108
Emneord [en]
BFT, Interswitch links, Leakage power, Noc
HSV kategori
Identifikatorer
URN: urn:nbn:se:kth:diva-152375DOI: 10.1109/ICECS.2009.5410930Scopus ID: 2-s2.0-77951466147ISBN: 978-142445091-6 (tryckt)OAI: oai:DiVA.org:kth-152375DiVA, id: diva2:755318
Konferanse
2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009, 13 December 2009 through 16 December 2009, Yasmine Hammamet, Tunisia
Merknad

QC 20141014

Tilgjengelig fra: 2014-10-14 Laget: 2014-09-26 Sist oppdatert: 2014-10-14bibliografisk kontrollert

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Totalt: 343 treff
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