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Network on Chip: Performance Bound and Tightness
KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
2015 (Engelska)Doktorsavhandling, monografi (Övrigt vetenskapligt)
Abstract [en]

Featured with good scalability, modularity and large bandwidth, Network-on-Chip (NoC) has been widely applied in manycore Chip Multiprocessor (CMP) and Multiprocessor System-on-Chip (MPSoC) architectures. The provision of guaranteed service emerges as an important NoC design problem due to the application requirements in Quality-of-Service (QoS).

Formal analysis of performance bounds plays a critical role in ensuring guaranteed service of NoC by giving insights into how the design parameters impact the network performance. The study in this thesis proposes analysis methods for delay and backlog bounds with Network Calculus (NC). Based on xMAS (eXecutable Micro-Architectural Specification), a formal framework to model communication fabrics, the delay bound analysis procedure is presented using NC. The micro-architectural xMAS representation of a canonical on-chip router is proposed with both the data flow and control flow well captured. Furthermore, a well-defined xMAS model for a specific application on an NoC can be created with network and flow knowledge and then be mapped to corresponding NC analysis model for end-to-end delay bound calculation. The xMAS model effectively bridges the gap between the informal NoC micro-architecture and the formal analysis model. Besides delay bound, the analysis of backlog bound is also crucial for predicting buffer dimensioning boundary in on-chip Virtual Channel (VC) routers. In this thesis, basic buffer use cases are identified with corresponding analysis models proposed so as to decompose the complex flow contention in a network. Then we develop a topology independent analysis technique to convey the backlog bound analysis step by step. Algorithms are developed to automate this analysis procedure.

Accompanying the analysis of performance bounds, tightness evaluation is an essential step to ensure the validity of the analysis models. However, this evaluation process is often a tedious, time-consuming, and manual simulation process in which many simulation parameters may have to be configured before the simulations run. In this thesis, we develop a heuristics aided tightness evaluation method for the analytical delay and backlog bounds. The tightness evaluation is abstracted as constrained optimization problems with the objectives formulated as implicit functions with respect to the system parameters. Based on the well-defined problems, heuristics can be applied to guide a fully automated configuration searching process which incorporates cycle-accurate bit-accurate simulations. As an example of heuristics, Adaptive Simulated Annealing (ASA) is adopted to guide the search in the configuration space. Experiment results indicate that the performance analysis models based on NC give tight results which are effectively found by the heuristics aided evaluation process even the model has a multidimensional discrete search space and complex constraints.

In order to facilitate xMAS modeling and corresponding validation of the performance analysis models, the thesis presents an xMAS tool developed in Simulink. It provides a friendly graphical interface for xMAS modeling and parameter configuring based on the powerful Simulink modeling environment. Hierarchical model build-up and Verilog-HDL code generation are essentially supported to manage complex models and conduct simulations. Attributed to the synthesizable xMAS library and the good extendibility, this xMAS tool has promising use in application specific NoC design based on the xMAS components.

Ort, förlag, år, upplaga, sidor
Stockholm: KTH Royal Institute of Technology, 2015. , s. xx, 147
Serie
TRITA-ICT-ECS AVH, ISSN 1653-6363 ; 15:30
Nyckelord [en]
Network-on-Chip, Performance analysis, Network Calculus
Nationell ämneskategori
Kommunikationssystem
Forskningsämne
Informations- och kommunikationsteknik
Identifikatorer
URN: urn:nbn:se:kth:diva-166412ISBN: 978-91-7595-531-5 (tryckt)OAI: oai:DiVA.org:kth-166412DiVA, id: diva2:810980
Disputation
2015-06-04, Sal/hall B, Elektrum , KTH-ICT, Isafjordsgatan 22, Kista, 09:00 (Engelska)
Opponent
Handledare
Anmärkning

QC 20150520

Tillgänglig från: 2015-05-20 Skapad: 2015-05-08 Senast uppdaterad: 2016-10-26Bibliografiskt granskad

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