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Optimization of a Compact I–V Model forGraphene FETs: Extending Parameter Scalability for Circuit Design Exploration
Technical University of Catalonia.
STMicroelectronics.
KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
University of Siegen.
Vise andre og tillknytning
2015 (engelsk)Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, nr 11, s. 3870-3875Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

An optimization of the current-to-voltage transfer characteristic of a graphene FET (GFET) compact model, based on drift-diffusion carrier transport, is presented. The improved accuracy at Dirac point extends the model usability for GFETs when scaling parameters, such as voltage supply, gate length, oxide thickness, and mobility, for circuit design exploration. The model's accuracy is demonstrated through fitting to GFETs processed in-house. The model has been written in a standard behavioral language, and extensively run in an analog circuit simulator for designing basic circuits, such as inverters and cascode cells, demonstrating its robustness.

sted, utgiver, år, opplag, sider
IEEE Press, 2015. Vol. 62, nr 11, s. 3870-3875
Emneord [en]
Circuit design, compact model, graphene FET (GFET), parameter extraction
HSV kategori
Forskningsprogram
Elektro- och systemteknik
Identifikatorer
URN: urn:nbn:se:kth:diva-177541DOI: 10.1109/TED.2015.2479036ISI: 000364242000063Scopus ID: 2-s2.0-84946122079OAI: oai:DiVA.org:kth-177541DiVA, id: diva2:873197
Prosjekter
GRADE
Forskningsfinansiär
EU, FP7, Seventh Framework Programme, 317839
Merknad

QC 20151130

Tilgjengelig fra: 2015-11-23 Laget: 2015-11-23 Sist oppdatert: 2017-12-01bibliografisk kontrollert

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Rusu, Ana

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