Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0002-8072-1742
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
2003 (English)In: Design, Automation And Test In Europe Conference And Exhibition, Proceedings , LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2003, 1126-1127 p.Conference paper, Published paper (Refereed)
Abstract [en]

In Networks on Chip, NoC, very low cost and high performance switches will be of critical importance. For a regular two-dimensional NoC we propose a very simple, memoryless switch. In case of congestion, packets are emitted in a non-ideal direction, also called deflective routing. To increase the maximum tolerable load of the network, we propose a Proximity Congestion Awareness, PCA, technique, where switches use load information of neighbouring switches, called stress values, for their own switching decisions, thus avoiding congested areas. We present simulation results with random traffic which show that the PCA technique can increase the maximum traffic load by a factor of over 20.

Place, publisher, year, edition, pages
LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2003. 1126-1127 p.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-5696DOI: 10.1109/DATE.2003.1253765ISI: 000182683800189ISBN: 0-7695-1870-2 (print)OAI: oai:DiVA.org:kth-5696DiVA: diva2:10145
Conference
Design, Automation and Test in Europe Conference and Exhibition (DATE 03), MUNICH, GERMANY, MAR 03-07, 2003
Note
QC 20101122Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2011-11-24Bibliographically approved
In thesis
1. Exploring trade-offs between Latency and Throughput in the Nostrum Network on Chip
Open this publication in new window or tab >>Exploring trade-offs between Latency and Throughput in the Nostrum Network on Chip
2006 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

During the past years has the Nostrum Network on Chip (NoC) been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties (IP) on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle.

Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly.

Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce

the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called Data Motorways achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in

hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks.

This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways

can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%.

Place, publisher, year, edition, pages
Kista: Mikroelektronik och informationsteknik, 2006. ix, 37 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 06:02
Keyword
Micro electronics, Nostrum, Network on Chip, NoC, on-chip networks, micro networks, Nätverk på kisel, Nätverk på chip
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-3949 (URN)
Presentation
2006-05-23, Sal E, Forum, Isafjordsgatan 22, Kista, 13:00
Opponent
Supervisors
Note
QC 20101122Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2010-11-22Bibliographically approved
2. Architectural Techniques for Improving Performance in Networks on Chip
Open this publication in new window or tab >>Architectural Techniques for Improving Performance in Networks on Chip
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The main aim of this thesis is to propose enhancing techniques for the performance in Networks on Chips. In addition, a concrete proposal for a protocol stack within our NoC platform Nostrum is presented. Nostrum inherently supports both Best Effort as well as Guaranteed Throughput traffic delivery. It employs a deflective routing scheme for best effort traffic delivery that gives a small footprint of the switches in combination with robustness to disturbances in the network. For the traffic delivery with hard guarantees a TDMA based scheme is used. During the transmission process in a NoC several stages are involved. In the papers included, I propose a set of strategies to enhance the performance in several of these stages. The strategies are summarised as follows

Temporally Disjoint Networks is that a physical network, potentially, can be seen to contain a set of separate networks that a packet can enter dependenton when it enters the physical network. This has the consequence that wecould have different traffic types in the different networks.

Looped containers provide means to set up virtual circuits in networksusing deflective routing. High priority container packets are inserted intothe network to follow a predefined, closed, route between source and destination.At sender side the packets are loaded and sent to the destination where it is unloaded and sent back.

Proximity Congestion Awareness reduces the load of the network by diverting packets away from congested areas. It can increase the maximum trafficload by a factor of 20.

Dual Packet Exit increases the exit bandwidth of the network leading to a50 percent reduction in worst-case latency and a 30 percent reduction inaverage latency as well as a lowered buffer usage.

Priority Based Forced Requeue prematurely lifts out low priority packetsfrom the network to be requeued. Packets that have not yet entered the network compete with packets inside the network which gives tighter boundson admission with a reduction of worst case latencies by 50 percent.

Furthermore, Operational Efficiency is proposed as a measure to quantifyhow effective a network is and is defined as the throughput per buffers used in the system. An increase of the injection of packets into the network to increase the system throughput will have a cost associated to it and can be optimised to save energy.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2011. xxiv, 103 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 11:13
National Category
Communication Systems
Identifiers
urn:nbn:se:kth:diva-48243 (URN)978-91-7501-169-1 (ISBN)
Public defence
2011-12-08, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 13:00 (English)
Opponent
Supervisors
Note
QC 20111124Available from: 2011-11-24 Created: 2011-11-16 Last updated: 2012-01-16Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full text

Authority records BETA

Öberg, Johnny

Search in DiVA

By author/editor
Nilsson, ErlandMillberg, MikaelÖberg, JohnnyJantsch, Axel
By organisation
Microelectronics and Information Technology, IMIT
Other Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 62 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf