Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Reducing Power and Latency in 2-D Mesh NoCs using Globally Pseudochronous Locally Synchronous Clocking
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0002-8072-1742
2004 (English)In:  International Conference On Hardware/Software Codesign And System Synthesis   , New York, USA: ASSOC COMPUTING MACHINERY , 2004, 176-181 p.Conference paper, Published paper (Refereed)
Abstract [en]

One of the main problems when designing large ASICs today is to distribute a low power synchronous clock over the whole chip and a lot of remedies to this problem has been proposed over the years. For Networks-on-Chip (NoC), where computational Resources are organised in a 2-D mesh connected together through Switches in an on-chip interconnection network, another possibility exists: Globally Pseudochronous Locally Synchronous clock distribution.

In this paper, we present a clocking scheme for NoCs that we call Globally Pseudochronous Locally Synchronous, in which we distribute a clock with a constant phase difference between he switches. As a consequence of the phase difference, some paths along the NoC switch network become faster than the others. We call these paths Data Motorways. By adapting the switching policy in the switches to prefer data to use the motorways, we show that the latency within the network is reduced with up to 40% compared to a synchronous reference case.

The phase difference between the resources also makes the circuit more tolerant to clock skew. It also distributes the current peaks more evenly across the clock period, which lead to a reduction in peak power, which in turn further reduces the clock skew and the jitter in the clock network.

Place, publisher, year, edition, pages
New York, USA: ASSOC COMPUTING MACHINERY , 2004. 176-181 p.
Keyword [en]
clocking, GALS, GPLS, mesh, network on chip, pseudochronous, hot-potato
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-5699ISI: 000225185600032Scopus ID: 2-s2.0-16244385949ISBN: 1-58113-937-3 (print)OAI: oai:DiVA.org:kth-5699DiVA: diva2:10148
Conference
2nd International Conference on Hardware/Software Codesign and Systems Synthesis, Stockholm, SWEDEN, SEP 08-10, 2004
Note
QC 20101122Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2010-11-22Bibliographically approved
In thesis
1. Exploring trade-offs between Latency and Throughput in the Nostrum Network on Chip
Open this publication in new window or tab >>Exploring trade-offs between Latency and Throughput in the Nostrum Network on Chip
2006 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

During the past years has the Nostrum Network on Chip (NoC) been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties (IP) on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle.

Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly.

Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce

the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called Data Motorways achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in

hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks.

This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways

can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%.

Place, publisher, year, edition, pages
Kista: Mikroelektronik och informationsteknik, 2006. ix, 37 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 06:02
Keyword
Micro electronics, Nostrum, Network on Chip, NoC, on-chip networks, micro networks, Nätverk på kisel, Nätverk på chip
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-3949 (URN)
Presentation
2006-05-23, Sal E, Forum, Isafjordsgatan 22, Kista, 13:00
Opponent
Supervisors
Note
QC 20101122Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2010-11-22Bibliographically approved

Open Access in DiVA

No full text

Scopus

Authority records BETA

Öberg, Johnny

Search in DiVA

By author/editor
Nilsson, ErlandÖberg, Johnny
By organisation
Microelectronics and Information Technology, IMIT
Other Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

isbn
urn-nbn

Altmetric score

isbn
urn-nbn
Total: 43 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf