Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Trading off Power versus Latency using GPLS Clocking in 2D-Mesh NoCs
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0002-8072-1742
2005 (English)In: Isscs 2005: International Symposium On Signals, Circuits And Systems, Vols 1 And 2, Proceedings , New York, USA: IEEE , 2005, 51-54 p.Conference paper, Published paper (Refereed)
Abstract [en]

To handle the design complexity when the number of transistors on-chip reaches one billion, new ways of organizing chips will be needed. One solution to this problem is to organize computational resources in a grid, where all communication between the resources are performed using an interconnection network. These networks are commonly referred to as Networks-on-Chip, or NoCs.

This paper focus on the trade-off between power and latency while keeping the required interconnection bandwidth constant. The clock frequency can be lowered to reduce the power, with reduced bandwidth as a consequence, which in a synchronous system will increase the latency linearly. In a 2D-Mesh NoC structure, it is possible to choose the regions with different clock phase and arrange them in such ways that the latency from sender to receiver along certain paths is nearly constant, and the total average latency is reduced with 50%. The reduction can then be exploited to trade off latency vs. power; the GPLS solution consumes 50% or the power compared to the fully synchronous solution, at the same latency and constant throughput.

Place, publisher, year, edition, pages
New York, USA: IEEE , 2005. 51-54 p.
Keyword [en]
Bandwidth, Electric clocks, Interconnection networks
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-5700DOI: 10.1109/ISSCS.2005.1509848ISI: 000231532900013Scopus ID: 2-s2.0-33749068644ISBN: 0-7803-9029-6 (print)OAI: oai:DiVA.org:kth-5700DiVA: diva2:10149
Conference
7th International Symposium on Signals, Circuits and Systems (ISSCS 2005), Iasi, ROMANIA, JUL 14-15, 2005
Note
QC 20101122Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2010-11-22Bibliographically approved
In thesis
1. Exploring trade-offs between Latency and Throughput in the Nostrum Network on Chip
Open this publication in new window or tab >>Exploring trade-offs between Latency and Throughput in the Nostrum Network on Chip
2006 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

During the past years has the Nostrum Network on Chip (NoC) been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties (IP) on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle.

Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly.

Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce

the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called Data Motorways achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in

hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks.

This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways

can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%.

Place, publisher, year, edition, pages
Kista: Mikroelektronik och informationsteknik, 2006. ix, 37 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 06:02
Keyword
Micro electronics, Nostrum, Network on Chip, NoC, on-chip networks, micro networks, Nätverk på kisel, Nätverk på chip
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-3949 (URN)
Presentation
2006-05-23, Sal E, Forum, Isafjordsgatan 22, Kista, 13:00
Opponent
Supervisors
Note
QC 20101122Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2010-11-22Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Authority records BETA

Öberg, Johnny

Search in DiVA

By author/editor
Nilsson, ErlandÖberg, Johnny
By organisation
Microelectronics and Information Technology, IMIT
Other Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 46 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf