Trading off Power versus Latency using GPLS Clocking in 2D-Mesh NoCs
2005 (English)In: Isscs 2005: International Symposium On Signals, Circuits And Systems, Vols 1 And 2, Proceedings , New York, USA: IEEE , 2005, 51-54 p.Conference paper (Refereed)
To handle the design complexity when the number of transistors on-chip reaches one billion, new ways of organizing chips will be needed. One solution to this problem is to organize computational resources in a grid, where all communication between the resources are performed using an interconnection network. These networks are commonly referred to as Networks-on-Chip, or NoCs.
This paper focus on the trade-off between power and latency while keeping the required interconnection bandwidth constant. The clock frequency can be lowered to reduce the power, with reduced bandwidth as a consequence, which in a synchronous system will increase the latency linearly. In a 2D-Mesh NoC structure, it is possible to choose the regions with different clock phase and arrange them in such ways that the latency from sender to receiver along certain paths is nearly constant, and the total average latency is reduced with 50%. The reduction can then be exploited to trade off latency vs. power; the GPLS solution consumes 50% or the power compared to the fully synchronous solution, at the same latency and constant throughput.
Place, publisher, year, edition, pages
New York, USA: IEEE , 2005. 51-54 p.
Bandwidth, Electric clocks, Interconnection networks
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-5700DOI: 10.1109/ISSCS.2005.1509848ISI: 000231532900013ScopusID: 2-s2.0-33749068644ISBN: 0-7803-9029-6OAI: oai:DiVA.org:kth-5700DiVA: diva2:10149
7th International Symposium on Signals, Circuits and Systems (ISSCS 2005), Iasi, ROMANIA, JUL 14-15, 2005
QC 201011222006-05-112006-05-112010-11-22Bibliographically approved