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Exploring trade-offs between Latency and Throughput in the Nostrum Network on Chip
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
2006 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

During the past years has the Nostrum Network on Chip (NoC) been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties (IP) on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle.

Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly.

Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce

the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called Data Motorways achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in

hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks.

This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways

can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%.

Place, publisher, year, edition, pages
Kista: Mikroelektronik och informationsteknik , 2006. , ix, 37 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 06:02
Keyword [en]
Micro electronics, Nostrum, Network on Chip, NoC, on-chip networks, micro networks
Keyword [sv]
Nätverk på kisel, Nätverk på chip
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-3949OAI: oai:DiVA.org:kth-3949DiVA: diva2:10151
Presentation
2006-05-23, Sal E, Forum, Isafjordsgatan 22, Kista, 13:00
Opponent
Supervisors
Note
QC 20101122Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2010-11-22Bibliographically approved
List of papers
1. Experiments of the Proximity Congestion Awareness with the Nostrum Backbone
Open this publication in new window or tab >>Experiments of the Proximity Congestion Awareness with the Nostrum Backbone
2003 (English)In: Proceedings of the Swedish System-on-Chip Conference (SSoCC), April 2003, 2003Conference paper, Published paper (Refereed)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-5695 (URN)
Conference
Swedish System-on-Chip Conference (SSoCC'03), Eskilstuna, Sweden, April 2003
Note
QC 20101122Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2010-11-22Bibliographically approved
2. Load Distribution with the Proximity Congestion Awareness in a Network on Chip
Open this publication in new window or tab >>Load Distribution with the Proximity Congestion Awareness in a Network on Chip
2003 (English)In: Design, Automation And Test In Europe Conference And Exhibition, Proceedings , LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2003, 1126-1127 p.Conference paper, Published paper (Refereed)
Abstract [en]

In Networks on Chip, NoC, very low cost and high performance switches will be of critical importance. For a regular two-dimensional NoC we propose a very simple, memoryless switch. In case of congestion, packets are emitted in a non-ideal direction, also called deflective routing. To increase the maximum tolerable load of the network, we propose a Proximity Congestion Awareness, PCA, technique, where switches use load information of neighbouring switches, called stress values, for their own switching decisions, thus avoiding congested areas. We present simulation results with random traffic which show that the PCA technique can increase the maximum traffic load by a factor of over 20.

Place, publisher, year, edition, pages
LOS ALAMITOS, USA: IEEE COMPUTER SOC, 2003
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-5696 (URN)10.1109/DATE.2003.1253765 (DOI)000182683800189 ()0-7695-1870-2 (ISBN)
Conference
Design, Automation and Test in Europe Conference and Exhibition (DATE 03), MUNICH, GERMANY, MAR 03-07, 2003
Note
QC 20101122Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2011-11-24Bibliographically approved
3. The Nostrum Backbone: a Communication Protocol Stack for Networks Chip
Open this publication in new window or tab >>The Nostrum Backbone: a Communication Protocol Stack for Networks Chip
Show others...
2004 (English)In: 17th International Conference On Vlsi Design, Proceedings - Design Methodologies For The Gigascale Era, LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2004, 693-696 p.Conference paper, Published paper (Refereed)
Abstract [en]

We propose a communication protocol stack to be used in Nostrum, our Network on Chip (NoC) architecture. In order to aid the designer in the selection process of what parts of protocols, and their respective facilities, to include, a layered approach to communication is taken. A nomenclature for describing the individual layers' interfaces and service definitions of the layers in the protocol stack is suggested,and used. The concept includes support for best effort traffic packet delivery as well as support for guaranteed bandwidth traffic, using virtual circuits. Furthermore an application to NoC adapter is defined, as part of the Resource to Network Interface, and is used to communicate between the Nostrum protocol stack and the application. An industrial example has been implemented, simulated, and the results justifies the suggested layered approach.

Place, publisher, year, edition, pages
LOS ALAMITOS, USA: IEEE COMPUTER SOC, 2004
Keyword
Adaptive control systems, Computer architecture, Interfaces (computer), Microprocessor chips, Network protocols, Packet networks, Programmable logic controllers, Virtual reality
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-5697 (URN)000189438600102 ()2-s2.0-2342620693 (Scopus ID)0-7695-2072-3 (ISBN)
Conference
17th International Conference on VLSI Design, Mumbai, INDIA, JAN 05-09, 2004
Note

QC 20101122

Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2014-12-11Bibliographically approved
4. Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip
Open this publication in new window or tab >>Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip
2004 (English)In: Design, Automation And Test In Europe Conference And Exhibition, Vols 1 And 2, Proceedings / [ed] Gielen G, Figueras J, LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2004, 890-895 p.Conference paper, Published paper (Refereed)
Abstract [en]

In today's emerging Network-on-Chips, there is a need for different traffic classes with different Quality-of-Service guarantees. Within our NoC architecture Nostrum, we have implemented a service of Guaranteed Bandwidth (GB), and latency, in addition to the already existing service of Best-Effort (BE) packet delivery. The guaranteed bandwidth is accessed via Virtual Circuits (VC). The vcs are implemented using a combination of two concepts that we call 'Looped Containers' and 'Temporally Disjoint Networks'. The Looped Containers are used to guarantee access to the network - independently of the current network load without dropping packets; and the TDNS are used in order to achieve several VCs, plus ordinary BE traffic, in the network. The TDNS are a consequence of the deflective routing policy used, and gives rise to an explicit time-division-multiplexing within the network. To prove our concept an HDL implementation has been synthesised and simulated. The cost in terms of additional hardware needed, as well as additional bandwidth is very low - less than 2 percent in both cases! Simulations showed that ordinary BE traffic is practically unaffected by the VCs.

Place, publisher, year, edition, pages
LOS ALAMITOS, USA: IEEE COMPUTER SOC, 2004
Keyword
Guaranteed bandwidth (GB), Looped Containers, Network-on-chips, Temporally Disjoint Networks
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-5698 (URN)10.1109/DATE.2004.1269001 (DOI)000189434000165 ()2-s2.0-3042740415 (Scopus ID)0-7695-2085-5 (ISBN)
Conference
Design, Automation and Test in Europe Conference and Exhibition (DATE 04), Paris, FRANCE, FEB 16-20, 2004
Note
QC 20101122. Titeln ändrad från "Guaranteed Throughput using Temporally Disjoint Networks in the Nostrum platform".Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2011-11-24Bibliographically approved
5. Reducing Power and Latency in 2-D Mesh NoCs using Globally Pseudochronous Locally Synchronous Clocking
Open this publication in new window or tab >>Reducing Power and Latency in 2-D Mesh NoCs using Globally Pseudochronous Locally Synchronous Clocking
2004 (English)In:  International Conference On Hardware/Software Codesign And System Synthesis   , New York, USA: ASSOC COMPUTING MACHINERY , 2004, 176-181 p.Conference paper, Published paper (Refereed)
Abstract [en]

One of the main problems when designing large ASICs today is to distribute a low power synchronous clock over the whole chip and a lot of remedies to this problem has been proposed over the years. For Networks-on-Chip (NoC), where computational Resources are organised in a 2-D mesh connected together through Switches in an on-chip interconnection network, another possibility exists: Globally Pseudochronous Locally Synchronous clock distribution.

In this paper, we present a clocking scheme for NoCs that we call Globally Pseudochronous Locally Synchronous, in which we distribute a clock with a constant phase difference between he switches. As a consequence of the phase difference, some paths along the NoC switch network become faster than the others. We call these paths Data Motorways. By adapting the switching policy in the switches to prefer data to use the motorways, we show that the latency within the network is reduced with up to 40% compared to a synchronous reference case.

The phase difference between the resources also makes the circuit more tolerant to clock skew. It also distributes the current peaks more evenly across the clock period, which lead to a reduction in peak power, which in turn further reduces the clock skew and the jitter in the clock network.

Place, publisher, year, edition, pages
New York, USA: ASSOC COMPUTING MACHINERY, 2004
Keyword
clocking, GALS, GPLS, mesh, network on chip, pseudochronous, hot-potato
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-5699 (URN)000225185600032 ()2-s2.0-16244385949 (Scopus ID)1-58113-937-3 (ISBN)
Conference
2nd International Conference on Hardware/Software Codesign and Systems Synthesis, Stockholm, SWEDEN, SEP 08-10, 2004
Note
QC 20101122Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2010-11-22Bibliographically approved
6. Trading off Power versus Latency using GPLS Clocking in 2D-Mesh NoCs
Open this publication in new window or tab >>Trading off Power versus Latency using GPLS Clocking in 2D-Mesh NoCs
2005 (English)In: Isscs 2005: International Symposium On Signals, Circuits And Systems, Vols 1 And 2, Proceedings , New York, USA: IEEE , 2005, 51-54 p.Conference paper, Published paper (Refereed)
Abstract [en]

To handle the design complexity when the number of transistors on-chip reaches one billion, new ways of organizing chips will be needed. One solution to this problem is to organize computational resources in a grid, where all communication between the resources are performed using an interconnection network. These networks are commonly referred to as Networks-on-Chip, or NoCs.

This paper focus on the trade-off between power and latency while keeping the required interconnection bandwidth constant. The clock frequency can be lowered to reduce the power, with reduced bandwidth as a consequence, which in a synchronous system will increase the latency linearly. In a 2D-Mesh NoC structure, it is possible to choose the regions with different clock phase and arrange them in such ways that the latency from sender to receiver along certain paths is nearly constant, and the total average latency is reduced with 50%. The reduction can then be exploited to trade off latency vs. power; the GPLS solution consumes 50% or the power compared to the fully synchronous solution, at the same latency and constant throughput.

Place, publisher, year, edition, pages
New York, USA: IEEE, 2005
Keyword
Bandwidth, Electric clocks, Interconnection networks
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-5700 (URN)10.1109/ISSCS.2005.1509848 (DOI)000231532900013 ()2-s2.0-33749068644 (Scopus ID)0-7803-9029-6 (ISBN)
Conference
7th International Symposium on Signals, Circuits and Systems (ISSCS 2005), Iasi, ROMANIA, JUL 14-15, 2005
Note
QC 20101122Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2010-11-22Bibliographically approved
7. PANACEA- A case study on the PANACEA NoC- a Nostrum Network on Chip prototype
Open this publication in new window or tab >>PANACEA- A case study on the PANACEA NoC- a Nostrum Network on Chip prototype
2006 (English)Report (Other academic)
Place, publisher, year, edition, pages
Stockholm: KTH, 2006
Series
TRITA-ICT/ECS R, ISSN 1653-7238 ; 06:01
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-5701 (URN)
Note
QC 20101122. Titeln ändrad från "A case study on the PANACEA NoC - a Nostrum Network on Chip prototype".Available from: 2006-05-11 Created: 2006-05-11 Last updated: 2010-11-22Bibliographically approved

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Citation style
  • apa
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  • ieee
  • modern-language-association-8th-edition
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  • de-DE
  • en-GB
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  • fi-FI
  • nn-NO
  • nn-NB
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  • Other locale
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Output format
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