A Three-Dimensional Networks-on-Chip Architecture with Dynamic Buffer Sharing
2016 (English)In: 2016 24TH EUROMICRO INTERNATIONAL CONFERENCE ON PARALLEL, DISTRIBUTED, AND NETWORK-BASED PROCESSING (PDP), 2016, 771-776 p.Conference paper (Refereed)
3D integration is a practical solution for overcoming the failure of Dennard scaling in future technology generations. This emerging technology stacks several die slices on top of each other on a single chip in order to provide higher-bandwidth and lower-latency than a 2D design due to extremely shorter inter-layer distances in the third dimension and. In this paper, we leverage the low latency vertical links to address buffer management, one of the most important design and management issues in Network-on-Chip(NoC). To this end, we present VerBuS, an architecture for 3D routers with Vertical BUffer Sharing capability enabled by ultra-low latency vertical links of a 3D chip. VerBuS can share virtual channels (VC) between vertically stacked routers. This way, the buffering capacity of a highly loaded router is increased by using idle VCs of vertically adjacent routers. Experimental results show up to 20% improvement in NoC performance metrics over state-of-the-art 3D router designs.
Place, publisher, year, edition, pages
2016. 771-776 p.
, Euromicro Conference on Parallel Distributed and Network-Based Processing, ISSN 1066-6192
Network-on-Chip, Dynamic resource sharing, 3D integration
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-193257DOI: 10.1109/PDP.2016.124ISI: 000381810900115ScopusID: 2-s2.0-84968756326ISBN: 978-1-4673-8776-7OAI: oai:DiVA.org:kth-193257DiVA: diva2:1033904
24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), FEB 17-19, 2016, Heraklion, GREECE
QC 201610102016-10-102016-09-302016-10-10Bibliographically approved