Memory-Access Aware DVFS for Network-on-Chip in CMPs
2016 (English)In: PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), IEEE conference proceedings, 2016, 1433-1436 p.Conference paper (Refereed)
We present a new DVFS technique for network-on-chip (NoC) that adjusts the voltage/frequency scales of routers according to memory-access characteristics of application running on the CMP. The memory characteristics are periodically profiled, reflecting both resource-access density in the network and memory-access criticality for application performance. The network conducts per-router voltage/frequency tuning using the memory-access density information while it performs priority-based switch allocation to speed up critical packets and avoid starvation using the memory-criticality information. Compared to a latest per-router DVFS approach, benchmark experiments demonstrate that our memory-access characteristics aware DVFS technique achieves not only better power saving, energy-delay product, but also enhanced network and application performance.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2016. 1433-1436 p.
, Design, Automation, and Test in Europe Conference and Exhibition, ISSN 1530-1591
IdentifiersURN: urn:nbn:se:kth:diva-193870ISI: 000382679200263ScopusID: 2-s2.0-84973621997ISBN: 978-3-9815-3707-9OAI: oai:DiVA.org:kth-193870DiVA: diva2:1034193
Design, Automation and Test in Europe Conference and Exhibition (DATE), MAR 14-18, 2016, Dresden, GERMANY
QC 201610112016-10-112016-10-112016-10-11Bibliographically approved