DVFS for NoCs in CMPs: A Thread Voting Approach
2016 (English)In: PROCEEDINGS OF THE 2016 IEEE INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE (HPCA-22), IEEE conference proceedings, 2016, 309-320 p.Conference paper (Refereed)
As the core count grows rapidly, dynamic voltage/frequency scaling (DVFS) in networks-on-chip (NoCs) becomes critical in optimizing energy efficacy in chip multiprocessors (CMPs). Previously proposed techniques often exploit inherent network-level metrics to do so. However, such network metrics may contradictorily reflect application's performance need, leading to power over/under provisioning. We propose a novel on-chip DVFS technique for NoCs that is able to adjust per-region V/F level according to voted V/F levels of communicating threads. Each region is composed of a few adjacent routers sharing the same V/F level. With a voting-based approach, threads seek to influence the DVFS decisions independently by voting for a preferred V/F level that best suits their own performance interest according to their runtime profiled message generation rate and data sharing characteristics. The vote expressed in a few bits is then carried in the packet header and spread to the routers on the packet route. The final DVFS decision is made democratically by a region DVFS controller based on the majority election result of collected votes from all active threads. To achieve scalable V/F adjustment, each region works independently, and the voting-based V/F tuning forms a distributed decision making process. We evaluate our technique with detailed simulations of a 64-core CMP running a variety of multi-threaded PARSEC benchmarks. Compared with a network without DVFS and a network metric (router buffer occupancy) based approach, experimental results show that our voting based DVFS mechanism improves the network energy efficacy measured in MPPJ (million packets per joule) by about 17.9% and 9.7% on average, respectively, and the system energy efficacy measured in MIPJ (million instructions per joule) by about 26.3% and 17.1% on average, respectively.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2016. 309-320 p.
, International Symposium on High-Performance Computer Architecture-Proceedings, ISSN 1530-0897
Computer Engineering Telecommunications
IdentifiersURN: urn:nbn:se:kth:diva-193871ISI: 000381808200026ISBN: 978-1-4673-9211-2OAI: oai:DiVA.org:kth-193871DiVA: diva2:1034196
22nd IEEE International Symposium on High-Performance Computer Architecture (HPCA), MAR 12-16, 2016, Barcelona, SPAIN
QC 201610112016-10-112016-10-112016-10-11Bibliographically approved