Fault-Tolerant 3-D Network-on-Chip Design using Dynamic Link Sharing
2016 (English)In: PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), IEEE conference proceedings, 2016, 1195-1200 p.Conference paper (Refereed)
The most important challenge in the emerging 3D integration technology is the higher temperature, particularly in the layers that are more distant from the heat sink, compared to planar 2D chips. High temperature, in turn, increases circuit's susceptibility to permanent and intermittent faults. On the other hand, the fast and high-bandwidth vertical links in the 3D integration technology have opened new horizons for network-on-chip (NoC) design innovations. In this paper, we leverage these ultra-low-latency vertical links to design a fault-tolerant 3D NoC architecture. In this architecture, permanent and intermittent defects on links and crossbars are bypassed by borrowing the idle bandwidth from vertically adjacent links and crossbars. Evaluation results under synthetic and realistic workloads show that the proposed fault-tolerance mechanism offers higher reliability and lower performance loss, when compared with state-of-the-art fault-tolerant 3D NoC designs.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2016. 1195-1200 p.
, Design, Automation, and Test in Europe Conference and Exhibition, ISSN 1530-1591
IdentifiersURN: urn:nbn:se:kth:diva-193869ISI: 000382679200223ScopusID: 2-s2.0-84973626759ISBN: 978-3-9815-3707-9OAI: oai:DiVA.org:kth-193869DiVA: diva2:1034203
Design, Automation and Test in Europe Conference and Exhibition (DATE), MAR 14-18, 2016, Dresden, GERMANY
QC 201610112016-10-112016-10-112016-10-11Bibliographically approved