Adaptive Fault Simulation on Many-core Microprocessor Systems
2015 (English)In: PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS), IEEE Computer Society, 2015, 151-154 p.Conference paper (Refereed)
Efficiency of Network-on-Chip based many-core microprocessors to implement parallel fault simulation methods for different circuit sizes is explored in this paper. We show that a naive and straightforward execution of fault simulation programs on such systems does not provide the maximum speedup due to severe bottlenecks in off-chip shared memory access at memory controllers. In order to exploit the available massive parallelism of homogenous many-core microprocessors, a runtime approach capable of adaptively balancing the load during the fault simulation process is proposed. We demonstrate the proposed adaptive fault simulation approach on a many-core platfonn, Intels Single-chip Cloud Computer showing up to 45X speedup compared to a serial fault simulation approach.
Place, publisher, year, edition, pages
IEEE Computer Society, 2015. 151-154 p.
Fault Simulation, Many-Core Systems, Load Balancing, Intel Single-chip Cloud Computer
IdentifiersURN: urn:nbn:se:kth:diva-193885DOI: 10.1109/DFT.2015.7315153ISI: 000380437100028ScopusID: 2-s2.0-8496279822ISBN: 978-1-5090-0312-9OAI: oai:DiVA.org:kth-193885DiVA: diva2:1039553
2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), OCT 12-14, 2015, Univ Massachusetts Amherst, Amherst, MA
QC 201610242016-10-242016-10-112016-10-24Bibliographically approved