A High-Level Thermal Model-Based Task Mapping for CMPs in Dark-Silicon Era
2016 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 9, 3406-3412 p.Article in journal (Refereed) Published
The chip multiprocessor (CMP) thermal issue impacting the system reliability and cooling cost has become a limiting factor for chip scaling and attracted growing attentions in the dark-silicon era. We propose a thermal-aware thread-to-core mapping method for CMPs under the dark-silicon constraint. We first propose a high-level spatial-temporal information-based thermal model to capture the relationship between the mapping result and the system thermal distribution. Then, we develop a thermal-aware mapping algorithm, which can automatically assign threads to proper cores based on the proposed model. Finally, we evaluate our method through simulations. Compared with three other mapping methods, namely, random, network-on-chip (NoC)-sprinting and round-robin, our thermal-priority design decreases the peak temperature by up to 4.31 K while showing good communication performance (34.7% of improvement against random and 50.3% against NoC sprinting, and only 6.3% of degradation against round robin); and our latency-priority design achieves the best communication performance with an improvement up to 62.6% and a satisfactory thermal profile.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2016. Vol. 63, no 9, 3406-3412 p.
Chip multiprocessor (CMP), dark silicon, network-on-chip (NoC), task mapping, thermal model
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-194476DOI: 10.1109/TED.2016.2592687ISI: 000384574400005ScopusID: 2-s2.0-84981714686OAI: oai:DiVA.org:kth-194476DiVA: diva2:1042020
FunderSwedish Research Council, E0509501
QC 201610312016-10-312016-10-282016-11-01Bibliographically approved