VisualNoC: A visualization and evaluation environment for simulation and mapping
2016 (English)In: ACM International Conference Proceeding Series, Association for Computing Machinery (ACM), 2016, 18-25 p.Conference paper (Refereed)
Simulation is the most common approach to evaluate Network on Chip (NoC) designs and many simulators at different abstraction levels have been developed so far. However, researchers have to spend a considerable amount of time and effort to debug, analyze, and extract meaningful information from the simulator reports. In this work, we propose a full-system visualization framework, called VisualNoC, that support both network simulation and task mapping. VisualNoC operates in a cycle-accurate mode and is based on an event-based trace model which can record the behaviors of routers, processing elements and packets. The visualization interface can provide efficient debugging and analysis platform by representing the simulation process and results in a variety of ways. One of the main features of VisualNoC is providing an intuitive way of analyzing the efficiency of different mapping algorithms that helps in finding bottlenecks and optimizing the design.
Place, publisher, year, edition, pages
Association for Computing Machinery (ACM), 2016. 18-25 p.
Debug, Many-core system, Mapping algorithm, Network-on-chip, Statistics, Visualization simulator, Conformal mapping, Embedded systems, Mapping, Program debugging, Routers, Servers, Simulators, Trace elements, Visualization, Many core, Mapping algorithms, Network simulation, Network-on-chip design, Processing elements, Simulation process, System visualization, Computer architecture
IdentifiersURN: urn:nbn:se:kth:diva-197218DOI: 10.1145/2934495.2949544ScopusID: 2-s2.0-84991104890OAI: oai:DiVA.org:kth-197218DiVA: diva2:1052955
4th ACM International Workshop on Many-Core Embedded Systems, MES 2016, 19 June 2016
QC 201612072016-12-072016-11-302016-12-07Bibliographically approved