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Exploring stacked main memory architecture for 3D GPGPUs
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0003-0061-3475
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2015 (English)In: Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015, IEEE conference proceedings, 2015Conference paper, Published paper (Refereed)
Abstract [en]

The tremendous number of threads on general purpose graphic processing units (GPGPUs) poses significant challenges on memory architecture design. 3D stacked main memory architecture atop GPGPU is a potential approach to provide high data communication bandwidth and low access latency to meet the requirement of GPGPUs. In this paper, we explore the performance of 3D GPGPUs with stacked main memory. The experimental results show that the 3D stacked GPGPU can provide up to 124.1% and on average 55.8% performance improvement compared to a 2D GPGPU scheme.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2015.
Keyword [en]
Program processors, Three dimensional integrated circuits, Access latency, Data-communication, General purpose graphic processing units, Main memory, Number of threads, Memory architecture
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:kth:diva-197130DOI: 10.1109/ASICON.2015.7516950Scopus ID: 2-s2.0-84982311227ISBN: 9781479984831 (print)OAI: oai:DiVA.org:kth-197130DiVA: diva2:1056243
Conference
11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, 3 November 2015 through 6 November 2015
Note

QC 20161214

Available from: 2016-12-14 Created: 2016-11-30 Last updated: 2016-12-14Bibliographically approved

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Publisher's full textScopushttp://ieeexplore.ieee.org/document/7516941/

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