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A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Fudan University, China.
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2016 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 63, no 12, p. 2245-2256Article in journal (Refereed) Published
Abstract [en]

Adapting the processor to the target application is essential in the Internet-of-Things (IoT), and thus requires customizability in order to improve energy efficiency and scalability to provide sufficient performance. In this paper, a reconfigurable and scalable control-centric architecture is proposed, and a processor consisting of two cores and an on-chip multi-mode router is implemented. Reconfigurability is enabled by a programmable sequence mapping table (SMT) which reorganizes functional units in each cycle, thus increasing hardware utilization and reducing excessive data movement for high energy efficiency. The router facilitates both wormhole and circuit switching to construct intra- or inter-chip interconnections, providing scalable performance. Fabricated in a 65-nm process, the chip exhibits 101.4 GOPS/W energy efficiency with a die size of 3.5 mm(2). The processor carries out general-purpose processing with a code size 29% smaller than the ARM Cortex M4, and improves the performance of application-specific processing by over ten times when implementing AES and RSA using SMTs instead of general-purpose C. By utilizing the on-chip router, the processor can be interconnected up to 256 nodes, with a single link bandwidth of 1.4 Gbps.

Place, publisher, year, edition, pages
IEEE, 2016. Vol. 63, no 12, p. 2245-2256
Keywords [en]
Control-centric design, dual cores, dual-mode router, energy-efficient processor, reconfigurable and scalable
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-199521DOI: 10.1109/TCSI.2016.2616363ISI: 000389338300015Scopus ID: 2-s2.0-85000405900OAI: oai:DiVA.org:kth-199521DiVA, id: diva2:1065783
Conference
IEEE International Symposium on Circuits and Systems (ISCAS), MAY 22-25, 2016, Montreal, CANADA
Note

QC 20170116

Available from: 2017-01-16 Created: 2017-01-09 Last updated: 2017-11-29Bibliographically approved

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Huan, YuxiangZheng, Li-rong

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