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Hierarchical Design of a Low Power Standing Wave Oscillator Based Clock Distribution Network
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
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2016 (English)In: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), IEEE conference proceedings, 2016Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a hierarchical clock interconnection network with two-level bufferless standing wave resonant clock distribution to minimize the clock power consumption in a synchronous system. The first level is a serpentine network which consists of many coupled standing wave oscillators to distribute clock signals in the whole chip area. The second level is a group of fishbone architectures connected to the standing wave oscillators to route clock signals in the local areas. A clock synthesis flow for the fishbone architecture is also introduced to enable design automation. This fishbone architecture is studied through a pipelined floating-point fused multiply-add module under 28nm standard CMOS process. Simulation results show that, this architecture can reduce more than 30% clock power consumption compared with a traditional buffered clock network.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2016.
Keywords [en]
Standing wave oscillator, Clock distribution network, Clock synthesis, Clock power
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-201281ISI: 000391620400024Scopus ID: 2-s2.0-85011019226ISBN: 978-1-5090-1095-0 (print)OAI: oai:DiVA.org:kth-201281DiVA, id: diva2:1074243
Conference
2nd IEEE Nordic Circuits and Systems Conference (NORCAS), NOV 01-02, 2016, Copenhagen, DENMARK
Note

QC 20170215

Available from: 2017-02-15 Created: 2017-02-15 Last updated: 2017-02-15Bibliographically approved

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Huan, YuxiangZou, ZhuoZheng, Lirong
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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
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  • Other locale
More languages
Output format
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  • asciidoc
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