Multi-bit Transient Fault Control for NoC Links Using 2D Fault Coding Method
2016 (English)In: 2016 TENTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), IEEE, 2016Conference paper (Refereed)
In deep nanometer scale, Network-on-Chip (NoC) links are more prone to multi-bit transient fault. Conventional ECC techniques brings heavy area, power, and timing overheads when correcting and detecting multiple transient faults. Therefore, a cost-effective ECC technique, named 2D fault coding method, is adopted to overcome the multi-bit transient fault issue of NoC links. Its key innovation is that the wires of a link are treated as its matrix appearance and light-weight Parity Check Coding (PCC) is performed on the matrix's two dimensions (horizontal matrix rows and vertical matrix columns). Horizontal PCCs and vertical PCCs work together to find the faults' position and then correct them by simply inverting them. The procedure of using the 2D fault coding method to protect a NoC link is proposed, its correction and detection capability is analyzed, and its hardware implementation is carried out. Comparative experiments show that the proposal can largely reduce the ECC hardware cost, have much higher fault detection coverage, maintain almost zero silent fault percentages, and have higher fault correction percentages normalized under the same area, demonstrating that it is cost-effective and suitable to the multi-bit transient fault control for NoC links.
Place, publisher, year, edition, pages
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-202496DOI: 10.1109/NOCS.2016.7579328ISI: 000392263800012ScopusID: 2-s2.0-84994634526ISBN: 978-1-4673-9030-9 OAI: oai:DiVA.org:kth-202496DiVA: diva2:1077775
10th IEEE/ACM International Symposium on Networks-on-Chip (NOCS), AUG 31-SEP 02, 2016, Nara, JAPAN
QC 201703012017-03-012017-03-012017-03-07Bibliographically approved