Integration of selective epitaxial growth of SiGe/Ge layers in 14nm node FinFETs
2016 (English)In: ECS Transactions, Electrochemical Society Inc. , 2016, no 8, 273-279 p.Conference paper (Refereed)
In this study, the process integration of SiGe selective epitaxy on source/drain and SiGe/Ge bilayers selectively epitaxy on replacement Si channel regions for 14 nm node FinFETs has been presented. The epi-quality, layer profile and strain amount of the selectively grown SiGe and Ge layers were also investigated by means of various characterization tools. A series of prebaking experiments were performed for different temperatures in order to in-situ clean the Si fins prior to the SiGe S/D epitaxy. It was also found that a SiGe layer with graded Ge content was deposited as the strain relaxed buffer (SRB) layer in the channel trench prior to the Ge layer filling in the small trenches to make the void defect free.
Place, publisher, year, edition, pages
Electrochemical Society Inc. , 2016. no 8, 273-279 p.
Characterization, Epitaxial growth, Germanium, MOSFET devices, Channel region, Characterization tools, Process integration, Selective epitaxial growth, Selective epitaxy, Selectively epitaxy, Strain-relaxed buffer layers, Void defects, Silicon alloys
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-201973DOI: 10.1149/07508.0273ecstScopusID: 2-s2.0-84991698876ISBN: 9781607685395 OAI: oai:DiVA.org:kth-201973DiVA: diva2:1078375
Symposium on SiGe, Ge, and Related Materials: Materials, Processing, and Devices 7 - PRiME 2016/230th ECS Meeting, 2 October 2016 through 7 October 2016
QC 201703032017-03-032017-03-032017-03-03Bibliographically approved