The impact of Moore's Law and loss of Dennard scaling: Are DSP SoCs an energy efficient alternative to x86 SoCs?
2016 (English)In: Journal of Physics, Conference Series, ISSN 1742-6588, E-ISSN 1742-6596, Vol. 762, no 1, 012022Article in journal (Refereed) Published
Moore's law, the doubling of transistors per unit area for each CMOS technology generation, is expected to continue throughout the decade, while Dennard voltage scaling resulting in constant power per unit area stopped about a decade ago. The semiconductor industry's response to the loss of Dennard scaling and the consequent challenges in managing power distribution and dissipation has been leveled off clock rates, a die performance gain reduced from about a factor of 2.8 to 1.4 per technology generation, and multi-core processor dies with increased cache sizes. Increased caches sizes offers performance benefits for many applications as well as energy savings. Accessing data in cache is considerably more energy efficient than main memory accesses. Further, caches consume less power than a corresponding amount of functional logic. As feature sizes continue to be scaled down an increasing fraction of the die must be "underutilized" or "dark" due to power constraints. With power being a prime design constraint there is a concerted effort to find significantly more energy efficient chip architectures than dominant in servers today, with chips potentially incorporating several types of cores to cover a range of applications, or different functions in an application, as is already common for the mobile processor market. Digital Signal Processors (DSPs), largely targeting the embedded and mobile processor markets, typically have been designed for a power consumption of 10% or less of a typical x86 CPU, yet with much more than 10% of the floating-point capability of the same technology generation x86 CPUs. Thus, DSPs could potentially offer an energy efficient alternative to x86 CPUs. Here we report an assessment of the Texas Instruments TMS320C6678 DSP in regards to its energy efficiency for two common HPC benchmarks: STREAM (memory system benchmark) and HPL (CPU benchmark).
Place, publisher, year, edition, pages
Institute of Physics (IOP), 2016. Vol. 762, no 1, 012022
Cache memory, Commerce, Computation theory, Digital arithmetic, Digital signal processors, Energy conservation, Program processors, Semiconductor device manufacture, Signal processing, Voltage scaling, Design constraints, Main-memory access, Mobile processors, Multi-core processor, Performance benefits, Power constraints, Power distributions, Semiconductor industry, Energy efficiency
IdentifiersURN: urn:nbn:se:kth:diva-202127DOI: 10.1088/1742-6596/762/1/012022ScopusID: 2-s2.0-85002497815OAI: oai:DiVA.org:kth-202127DiVA: diva2:1079406
18 January 2016 through 22 January 2016
QC 201703082017-03-082017-03-082017-03-08Bibliographically approved