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Enabling Area Efficient RF ICs through Monolithic 3D Integration
KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.ORCID iD: 0000-0002-7534-9317
KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
KTH, School of Information and Communication Technology (ICT), Electronics.
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2017 (English)In: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, 610-613 p., 7927059Conference paper, Published paper (Refereed)
Abstract [en]

The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2017. 610-613 p., 7927059
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Information and Communication Technology
Identifiers
URN: urn:nbn:se:kth:diva-203348DOI: 10.23919/DATE.2017.7927059ISI: 000404171500111Scopus ID: 2-s2.0-85020197871ISBN: 9783981537093 (print)OAI: oai:DiVA.org:kth-203348DiVA: diva2:1082052
Conference
20th Design, Automation and Test in Europe, DATE 2017, SwissTech Convention Center, Swisstech, Lausanne, Switzerland, 27 March 2017 through 31 March 2017
Funder
Swedish Foundation for Strategic Research , 76197
Note

QC 20170626

Available from: 2017-03-15 Created: 2017-03-15 Last updated: 2017-08-02Bibliographically approved

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Rodriguez, Saul

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