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ACO-Based Thermal-Aware Thread-to-Core Mapping for Dark-Silicon-Constrained CMPs
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2017 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, no 3, 930-937 p.Article in journal (Refereed) Published
Abstract [en]

The limitation on thermal budget in chip multiprocessor (CMP) results in a fraction of inactive silicon regions called dark silicon, which significantly impacts the system performance. In this paper, we propose a thread-to-core mapping method for dark-silicon-constrainedCMPs to address their thermal issue. We first propose a thermal predictionmodel to forecast CMP temperature after the CMP executes a forthcoming application. Then, we develop an ant colony optimization-based algorithm to conduct the thread-to- core mapping process, such that the CMP peak temperature is minimized and, consequently, the probability of triggering CMP dynamic thermal management is decreased. Finally, we evaluate our method and compare it with the baseline (a standard Linux scheduler) and other existing methods (NoC-Sprinting, DaSiM mapping, and TP mapping). The simulation results show that our method gains good thermal profile and computational performance, and performs well with chip scaling. Specifically, it eliminates all thermal emergency time, outperforming all other methods, and gains million instructions per second improvement up to 12.9% against the baseline.

Place, publisher, year, edition, pages
IEEE Press, 2017. Vol. 64, no 3, 930-937 p.
Keyword [en]
Chip multiprocessor (CMP), dark silicon, thermal model, thread-to-core mapping
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:kth:diva-204059DOI: 10.1109/TED.2017.2653838ISI: 000396056700030Scopus ID: 2-s2.0-85011294756OAI: oai:DiVA.org:kth-204059DiVA: diva2:1085721
Note

QC 20170330

Available from: 2017-03-30 Created: 2017-03-30 Last updated: 2017-03-30Bibliographically approved

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Lu, Zhonghai
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CiteExportLink to record
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Citation style
  • apa
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