Advances in Functional Decomposition: Theory and Applications
2006 (English)Doctoral thesis, comprehensive summary (Other academic)
Functional decomposition aims at finding efficient representations for Boolean functions. It is used in many applications, including multi-level logic synthesis, formal verification, and testing.
This dissertation presents novel heuristic algorithms for functional decomposition. These algorithms take advantage of suitable representations of the Boolean functions in order to be efficient.
The first two algorithms compute simple-disjoint and disjoint-support decompositions. They are based on representing the target function by a Reduced Ordered Binary Decision Diagram (BDD). Unlike other BDD-based algorithms, the presented ones can deal with larger target functions and produce more decompositions without requiring expensive manipulations of the representation, particularly BDD reordering.
The third algorithm also finds disjoint-support decompositions, but it is based on a technique which integrates circuit graph analysis and BDD-based decomposition. The combination of the two approaches results in an algorithm which is more robust than a purely BDD-based one, and that improves both the quality of the results and the running time.
The fourth algorithm uses circuit graph analysis to obtain non-disjoint decompositions. We show that the problem of computing non-disjoint decompositions can be reduced to the problem of computing multiple-vertex dominators. We also prove that multiple-vertex dominators can be found in polynomial time. This result is important because there is no known polynomial time algorithm for computing all non-disjoint decompositions of a Boolean function.
The fifth algorithm provides an efficient means to decompose a function at the circuit graph level, by using information derived from a BDD representation. This is done without the expensive circuit re-synthesis normally associated with BDD-based decomposition approaches.
Finally we present two publications that resulted from the many detours we have taken along the winding path of our research.
Place, publisher, year, edition, pages
Stockholm: KTH , 2006. , xi,176 p.
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 06:06
computer science, electronic system design, Boolean decomposition, binary decision diagram, logic synthesis, graph algorithm
IdentifiersURN: urn:nbn:se:kth:diva-4135OAI: oai:DiVA.org:kth-4135DiVA: diva2:10887
2006-10-12, E, KTH Forum, Isafjordsgatan 39, Kista, 09:00
Muzio, Jon, Professor
QC 201009092006-10-092006-10-092010-09-09Bibliographically approved
List of papers