Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Method for the wafer-level integration of shape memory alloy wires
KTH, School of Electrical Engineering (EES), Micro and Nanosystems.ORCID iD: 0000-0002-0525-8647
KTH, School of Electrical Engineering (EES), Micro and Nanosystems.ORCID iD: 0000-0003-3452-6361
2013 (English)Patent (Other (popular science, discussion, etc.))
Abstract [en]

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

Place, publisher, year, edition, pages
2013.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-206188OAI: oai:DiVA.org:kth-206188DiVA, id: diva2:1091750
Patent
US US 9054224 B2 (2015-06-09)
Note

QC 20170614

Available from: 2017-04-27 Created: 2017-04-27 Last updated: 2017-06-14Bibliographically approved

Open Access in DiVA

No full text in DiVA

Search in DiVA

By author/editor
Niklaus, FrankFischer, Andreas C.
By organisation
Micro and Nanosystems
Engineering and Technology

Search outside of DiVA

GoogleGoogle Scholar

urn-nbn

Altmetric score

urn-nbn
Total: 25 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf