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Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors
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2017 (English)In: Nanoscale Research Letters, ISSN 1931-7573, E-ISSN 1556-276X, Vol. 12, 123Article in journal (Refereed) Published
Abstract [en]

In this study, the integration of SiGe selective epitaxy on source/drain regions and high-k and metal gate for 22 nm node bulk pMOS transistors has been presented. Selective Si1-xGex growth (0.35 <= x <= 0.40) with boron concentration of 1-3 x 10(20) cm(-3) was used to elevate the source/drain. The main focus was optimization of the growth parameters to improve the epitaxial quality where the high-resolution x-ray diffraction (HRXRD) and energy dispersive spectrometer (EDS) measurement data provided the key information about Ge profile in the transistor structure. The induced strain by SiGe layers was directly measured by x-ray on the array of transistors. In these measurements, the boron concentration was determined from the strain compensation of intrinsic and boron-doped SiGe layers. Finally, the characteristic of transistors were measured and discussed showing good device performance.

Place, publisher, year, edition, pages
Springer, 2017. Vol. 12, 123
Keyword [en]
22-nm PMOS, SiGe selective epitaxy, RPCVD, High-k and metal gate
National Category
Nano Technology
Identifiers
URN: urn:nbn:se:kth:diva-204690DOI: 10.1186/s11671-017-1908-0ISI: 000394542800004PubMedID: 28228008ScopusID: 2-s2.0-85013155553OAI: oai:DiVA.org:kth-204690DiVA: diva2:1105155
Note

QC 20170602

Available from: 2017-06-02 Created: 2017-06-02 Last updated: 2017-06-02Bibliographically approved

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