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TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs
KTH.
KTH, School of Information and Communication Technology (ICT), Electronics.
KTH, School of Information and Communication Technology (ICT), Electronics.
2017 (English)In: Proceedings - 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Institute of Electrical and Electronics Engineers (IEEE), 2017, 92-99 p., 7833431Conference paper (Refereed)
Abstract [en]

In the nano scale era, the upcoming design challenges like dark silicon, power wall, and memory wall have prompted extensive research into the architectural alternatives to the general purpose processor. Coarse Grained Reconfig-urable Architectures (CGRAs) are emerging as one of the promising alternatives. Commonly, CGRAs are composed of a computation layer and a memory layer. Tempted by higher platform utilization and energy efficiency, recently proposed CGRAs offer dynamic remapping and parallelism. However, the existing works only address the computational elements, while for many applications the bulk of energy is consumed by the memory and memory accesses. Therefore, without architectural support to optimize the memory contents, according to the changes in computational layer, the benefits promised by dynamic parallelism and remapping are severely degraded. As a solution to this problem we present TransMem, a supporting memory infrastructure that complements the dynamic remapping and parallelism in the computational fabric. Simulation results reveal that the additional flexibility enhances the energy efficiency by up to 85% for the tested applications, compared to state of the art. Post-layout analysis reveals that TransMem incurs only 4% area penalty.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2017. 92-99 p., 7833431
Series
International Workshop on Power and Timing Modeling Optimization and Simulation, ISSN 2474-5456
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:kth:diva-208444DOI: 10.1109/PATMOS.2016.7833431ISI: 000401809900018ScopusID: 2-s2.0-85014097165ISBN: 9781509007332 OAI: oai:DiVA.org:kth-208444DiVA: diva2:1107201
Conference
26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, 21 September 2016 through 23 September 2016
Note

QC 20170609

Available from: 2017-06-09 Created: 2017-06-09 Last updated: 2017-06-12Bibliographically approved

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CiteExportLink to record
Permanent link

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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
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More languages
Output format
  • html
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  • asciidoc
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