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Optimization of Selective Growth of SiGe for Source/Drain in 14nm and beyond Nodes FinFETs
KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
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2017 (English)In: International Journal of High Speed Electronics and Systems, ISSN 0129-1564, Vol. 26, no 1-2, 1740003Article in journal (Refereed) Published
Abstract [en]

In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 1020 cm-3. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.

Place, publisher, year, edition, pages
World Scientific Publishing Co. Pte Ltd , 2017. Vol. 26, no 1-2, 1740003
Keyword [en]
FinFET, selective epitaxy growth, SiGe, Aspect ratio, Budget control, Epitaxial growth, Fins (heat exchange), Germanium, Hafnium oxides, High-k dielectric, Mapping, MOSFET devices, Silicon alloys, Synchrotron radiation, Tungsten, Boron concentrations, Electrical characteristic, High aspect ratio, Reciprocal space mapping, Strain distributions, Transistor structure, Atomic layer deposition
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-207307DOI: 10.1142/S0129156417400031ScopusID: 2-s2.0-85013290773OAI: oai:DiVA.org:kth-207307DiVA: diva2:1108864
Note

QC 20170613

Available from: 2017-06-13 Created: 2017-06-13 Last updated: 2017-06-13Bibliographically approved

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