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Silicon Carbide DTL, TTL and ECL Bipolar Integrated Circuits for High Temperature Computing
KTH, School of Information and Communication Technology (ICT).
2015 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Today, the availability of integrated circuits operating at high temperatures appears to be an increasingly important priority for a number of companies operating in various business sectors such as automotive, aviation, aerospace and oil and gas drilling. Since using silicon for this request is not feasible the research was channeled towards the discovery of new semiconductors more suitable to work at high temperature such as Silicon Carbide.

Numerous research that have been done have allowed to extrapolate the main characteristics of the material, however, a central processing unit (CPU) does not yet exist completely in Silicon Carbide; so the main challenge is to develop a CPU entirely in this material.

Main objective of this thesis is to model, analyze and layout basic digital gates and flip flop in Silicon Carbide in order to analyze the possible implementation of a CPU.

The aim of this work is to investigate, through simulation softwares such as LTSpice and Cadence, the functionality of these schematics in a wide range of temperatures [27°C-300°C] and to analyze the area occupied by a possible CPU. Every gate will be made with bipolar transistors, then the patterns will be modeled in three different logics: Diode-Transistor-Logic, Transistor-Transistor-Logic and Emitter-Coupled- Logic, so as to analyze for each of them the positive and negative aspects.

The final results have confirmed the expectations placed in the material in question since the simulated gates fulfill the requirements up to 300°C. A first layout shows, in best case using a TTL, an occupied area of 105 mm2using 3259 transistors while in DTL and ECL the layouts obtained are respectively of 122 mm2 and 174 mm2. The first estimate could be improved by optimizing the layout.

Place, publisher, year, edition, pages
2015. , 147 p.
Series
TRITA-ICT-EX, 2015:182
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-209135OAI: oai:DiVA.org:kth-209135DiVA: diva2:1110184
External cooperation
UNIVERSITY OF NAPLES FEDERICO II
Subject / course
Electrical Engineering
Educational program
Degree of Master
Examiners
Available from: 2017-06-15 Created: 2017-06-15 Last updated: 2017-06-21Bibliographically approved

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