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SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems
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2017 (English)In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 52, 89-105 p.Article in journal (Refereed) Published
Abstract [en]

With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER1.

Place, publisher, year, edition, pages
Elsevier, 2017. Vol. 52, 89-105 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-209877DOI: 10.1016/j.micpro.2017.05.016ISI: 000407984000009Scopus ID: 2-s2.0-85020444096OAI: oai:DiVA.org:kth-209877DiVA: diva2:1115198
Note

QC 20170626

Available from: 2017-06-26 Created: 2017-06-26 Last updated: 2017-09-12Bibliographically approved

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