Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Queueing Behavior and Packet Delays in Network Processor Systems
KTH, School of Electrical Engineering (EES), Communication Networks.
KTH, School of Computer Science and Communication (CSC), Numerical Analysis and Computer Science, NADA.
KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre. KTH, School of Electrical Engineering (EES), Communication Networks.ORCID iD: 0000-0002-3704-1338
2007 (English)In: 15th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems: Bogazici Univ, Dept Comp Engn, Istanbul, TURKEY, OCT 24-26, 2007 / [ed] Caglayan M. U.; Field AJ; Gelenbe E., 2007, 217-224 p.Conference paper, Published paper (Refereed)
Abstract [en]

Network processor systems provide the performance of ASICs combined withthe programmability of general-purpose processors. One of the main challengesin designing these systems is the memory subsystem used when forwarding andqueueing packets. In this work, we study the queueing behavior and packet delaysin a network processor system which works as a router. We introduce a systemmodel and a simulation tool based on the model. Using the simulation tool, bothbest-effort and diffserv IPv4 forwarding were modeled and tested using real-worldand synthetically generated packet traces. The results on queueing behavior havebeen used to dimension various queues, and can be used as guidelines for designingmemory subsystems and queueing disciplines. In particular, a system withsmall queue sizes has been proposed. The results on packet delays also show thatour diffserv setup provides good service differentiation for best-effort and prioritypackets. Finally, the study reveals that the choice of traces has a large impact onthe results when evaluating router and switch architectures.

Place, publisher, year, edition, pages
2007. 217-224 p.
Series
International Symposium on Modeling Analysis and Simulation of Computer and Telecommunication Systems Proceedings, ISSN 1526-7539
Keyword [en]
network processor; router; queueing behavior
National Category
Telecommunications
Identifiers
URN: urn:nbn:se:kth:diva-9330DOI: 10.1109/MASCOTS.2007.56ISI: 000265212400031Scopus ID: 2-s2.0-57849125895ISBN: 978-1-4244-1853-4 (print)OAI: oai:DiVA.org:kth-9330DiVA: diva2:113511
Note
QC 20100726Available from: 2008-10-20 Created: 2008-10-20 Last updated: 2013-09-09Bibliographically approved
In thesis
1. On the Design of Next-Generation Routers and IP Networks
Open this publication in new window or tab >>On the Design of Next-Generation Routers and IP Networks
2008 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

This thesis investigates distributed router architectures and IP networks with centralized control. While the current trend in IP-router architectures is towards decentralized design, there have also been research proposals for centralizing the control functions in IP networks. With continuous evolution of routers and IP networks, we believe that eventually IP networks in an autonomous system (AS) and a distributed router might converge into one network system. This system, which can be considered both as a distributed router and a centrally-controlled IP network, is divided into a control plane and a forwarding plane. The control plane is responsible for routing, management and signalling protocols, while the forwarding plane is responsible for forwarding packets.

The work in this thesis covers both the forwarding and control planes. In the forwarding plane, we study network processor systems that function as forwarding elements in a distributed router. We introduce a system model and a simulation tool based on the model. Using the simulation tool, we investigate network processor system design by studying throughput, utilization, queueing behavior and packet delays. In addition to network processor systems, we study IP-address lookup, which is one of the key packet processing functions in Internet routers. Our work in IP-address lookup contains an efficient lookup algorithm, a scheme to divide the lookup procedure into two-stages in a distributed router, and an approach to perform efficient lookup on a router supporting multiple virtual routers.

In the control plane, we study three emerging research issues with centralized control. We provide a thorough study of the routing convergence process in networks with centralized control, and compare it with decentralized link-state routing protocols. We propose an efficient approach to perform traffic engineering and routing in networks with centralized control, and compare it with an approach using optimized link weights. Finally, we present an approach to perform loop-free updates of forwarding tables when the forwarding paths change. This loop-free update approach is particularly useful in networks with centralized control.

The results presented in this thesis are useful for building next-generation routers and IP networks with centralized control that might eventually converge into one network system.

Place, publisher, year, edition, pages
Stockholm: KTH, 2008. vii, 34 p.
Series
Trita-EE, ISSN 1653-5146 ; 2008:040
Keyword
router architecture, IP-network architecture
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-9381 (URN)
Public defence
2008-11-26, M1, KTH, Stockholm, 14:00 (English)
Opponent
Supervisors
Note
QC 20100726Available from: 2008-11-03 Created: 2008-10-28 Last updated: 2010-07-26Bibliographically approved
2. Design and evaluation of network processor systems and forwarding applications
Open this publication in new window or tab >>Design and evaluation of network processor systems and forwarding applications
2006 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

During recent years, both the Internet traffic and packet transmission rates have been growing rapidly, and new Internet services such as VPNs, QoS and IPTV have emerged. To meet increasing line speed requirements and to support current and future Internet services, improvements and changes are needed in current routers both with respect to hardware architectures and forwarding applications. High speed routers are nowadays mainly based on application specific integrated circuits (ASICs), which are custom made and not flexible enough to support diverse services. Generalpurpose processors offer flexibility, but have difficulties to in handling high data rates. A number of software IP-address lookup algorithms have therefore been developed to enable fast packet processing in general-purpose processors. Network processors have recently emerged to provide the performance of ASICs combined with the programmability of general-purpose processors.

This thesis provides an evaluation of router design including both hardware architectures and software applications. The first part of the thesis contains an evaluation of various network processor system designs. We introduce a model for network processor systems which is used as a basis for a simulation tool. Thereafter, we study two ways to organize processing elements (PEs) inside a network processor to achieve parallelism: a pipelined and a pooled organization. The impact of using multiple threads inside a single PE is also studied. In addition, we study the queueing behavior and packet delays in such systems. The results show that parallelism is crucial to achieving high performance,but both the pipelined and the pooled processing-element topologies achieve comparable performances. The detailed queueing behavior and packet delay results have been used to dimension queues, which can be used as guidelines for designing memory subsystems and queueing disciplines.

The second part of the thesis contains a performance evaluation of an IP-address lookup algorithm, the LC-trie. The study considers trie search depth, prefix vector access behavior, cache behavior, and packet lookup service time. For the packet lookup service time, the evaluation contains both experimental results and results obtained from a model. The results show that the LC-trie is an efficient route lookup algorithm for general-purpose processors, capable of performing 20 million packet lookups per second on a Pentium 4, 2.8 GHz computer, which corresponds to a 40 Gb/s link for average sized packets. Furthermore, the results show the importance of choosing packet traces when evaluating IP-address lookup algorithms: real-world and synthetically generated traces may have very different behaviors.

The results presented in the thesis are obtained through studies of both hardware architectures and software applications. They could be used to guide the design of next-generation routers.

Place, publisher, year, edition, pages
Stockholm: KTH, 2006. vii, 15 p.
Series
Trita-EE, ISSN 1653-5146 ; 2006:054
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-4248 (URN)
Presentation
2006-12-19, Q2, KTH, Osquldas väg 10, Stockholm, 14:00
Opponent
Supervisors
Note
QC 20101112Available from: 2006-12-19 Created: 2006-12-19 Last updated: 2010-11-12Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Authority records BETA

Karlsson, Gunnar

Search in DiVA

By author/editor
Fu, JingHagsand, OlofKarlsson, Gunnar
By organisation
Communication NetworksNumerical Analysis and Computer Science, NADAACCESS Linnaeus Centre
Telecommunications

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 138 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf