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Impact of Traps and Strain on Optimized n- and p-Type TFETs Integrated on the Same InAs/AlGaSb Technology Platform
KTH, School of Engineering Sciences (SCI), Applied Physics.
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2017 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, no 8, p. 3108-3113Article in journal (Refereed) Published
Abstract [en]

A simulation study on the impact of interface traps and strain on the I -V characteristics of co-optimized p-and n-type tunnel FETs (TFETs) realized on the same InAs/Al0.05Ga0.95Sb technology platform is carried out, using a full-quantum ballistic simulator. In order to capture the effect of interface/border traps on the device electrostatics consistently with carrier degeneracy and ballistic transport, the classical Shockley-Read-Hall theory has been properly generalized. The effect of an experimental Dit distribution of a high-k gate stacks on InAs has been investigated. Unfortunately, traps induce a significant reduction of the ON-state current. However, it turns out that localized strain at the source/channel heterojunction caused by lattice mismatch is able to induce for the n-type TFET, a performance enhancement with respect to the ideal device even in the presence of traps. On the contrary, for the p-type one, a current degradation similar or equal to 18% is observed.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2017. Vol. 64, no 8, p. 3108-3113
Keywords [en]
III-V materials, interface traps (ITs), quantum transport, strain, tunnel FETs (TFET)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-212617DOI: 10.1109/TED.2017.2711779ISI: 000406268900009Scopus ID: 2-s2.0-85021810753OAI: oai:DiVA.org:kth-212617DiVA, id: diva2:1135938
Note

QC 20170824

Available from: 2017-08-24 Created: 2017-08-24 Last updated: 2018-09-19Bibliographically approved

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CiteExportLink to record
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  • apa
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  • de-DE
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Output format
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