A High-end Reconfigurable Computation Platform for Particle Physics Experiments
2008 (English)Licentiate thesis, monograph (Other scientific)
Modern nuclear and particle physics experiments run at a very high reaction rate and are able to deliver a data rate of up to hundred GBytes/s. This data rate is far beyond the storage and on-line analysis capability. Fortunately physicists have only interest in a very small proportion among the huge amounts of data. Therefore in order to select the interesting data and reject the background by sophisticated pattern recognition processing, it is essential to realize an efficient data acquisition and trigger system which results in a reduced data rate by several orders of magnitude. Motivated by the requirements from multiple experiment applications, we are developing a high-end reconfigurable computation platform for data acquisition and triggering. The system consists of a scalable number of compute nodes, which are fully interconnected by high-speed communication channels. Each compute node features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytesDDR2 memory. A hardware/software co-design approach is proposed to develop custom applications on the platform, partitioning performance-critical calculation to the FPGA hardware fabric while leaving flexible and slow controls to the embedded CPU plus the operating system. The system is expected to be high-performance and general-purpose for various applications especially in the physics experiment domain.
As a case study, the particle track reconstruction algorithm for HADES has been developed and implemented on the computation platform in the format of processing engines. The Tracking Processing Unit (TPU) recognizes peak bins on the projection plane and reconstructs particle tracks in realtime. Implementation results demonstrate its acceptable resource utilization and the feasibility to implement the module together with the sys-tem design on the FPGA. Experimental results show that the online track reconstruction computation achieves 10.8 - 24.3 times performance acceleration per TPU module when compared to the software solution on a Xeon2.4 GHz commodity server.
Place, publisher, year, edition, pages
Stockholm: KTH , 2008. , xiv, 66 p.
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 08:08
reconfigurable computing, FPGA implementation, HW/SW co-design, pattern recognition, particle physics
IdentifiersURN: urn:nbn:se:kth:diva-9360ISBN: 978-91-7415-145-9OAI: oai:DiVA.org:kth-9359DiVA: diva2:113609
2008-11-21, N1, Isafjordsgatan 28 A/D, KTH-Electrum, Kista, 09:00 (English)
Lindh, Lennart, Associate Professor
Jantsch, Axel, ProfessorLu, Zhonghai, Dr.Kuehn, Wolfgang, Professor
QC 201011182008-11-132008-10-222010-11-18Bibliographically approved