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Integrated Frequency Synthesis for Convergent Wireless Solutions
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2008 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Wireless transceivers combining several standards in one unit are of key importance. In order to reach the ultimate goal of maximizing the performance-to-cost ratio of such modules, a careful study of the target application, the architecture, and the frequency planning is strongly required. One of the most challenging tasks is the implementation of the frequency synthesizer. This challenge is compounded by the traditional technical difficulties in designing frequency synthesizers as well as the new requirements that include multi-standard support. As a result, studying the upper levels of the communication system becomes mandatory in order to frame the requirements of the frequency synthesizer and to provide a viable solution from a user’s perspective for an always-best-connected scenario. Additionally, the study of the upper layers opens up new opportunities for innovation at the lower layers, especially at the physical layer where the view is traditionally restricted by some harsh requirements whose source might not be clear at least for the physical-level designer. The first aim of this work is to provide a holistic view of how an optimum user experience can be achieved and how this affects the design of frequency synthesizers for the next generation networks. The work is heavily based on the existing garden of wireless standards although it can also serve for other applications such as real software-defined radios and dynamic spectrum allocation. As a result, this work cuts a vertical path starting from the best user experience vision down to the physical layer where it expands on the design of the frequency synthesizer. It proposes a wireless front-end solution that can make the vision of an always-best-connected scenario a reality. The architecture is based on a wireless detector called Sniffer that searches for an alternative connection while the main connection is running. Not only is the Sniffer solution viable at the physical level, but it also provides a stepping stone for development towards fully-enabled multi-standard transceivers. After this, and inline with the previous vision, some important frequency synthesizer parameters are pointed out and enhancements on the phase-locked architectures are presented. This includes ways to extend the range of the frequency synthesizer and ways to make the synthesizer adaptable depending on the requirements of the wireless standards. This work leads directly to the implementation of a multi-standard frequency synthesizer where the details of the top-down design procedure are presented at several levels of abstraction. In order to round-up the work, and due to the fact that the requirements of the frequency synthesizer stretch thin the capabilities of the technology used, calibration techniques to increase the yield of such a complicated sub-system are presented, an important step towards first-pass success.

Place, publisher, year, edition, pages
Stockholm: KTH , 2008. , xviii, 182 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 08:07
Keyword [en]
wireless, transceiver, Bluetooth, DECT, GSM, 3G, LTE, WLAN, WiMAX, multi-standard, vertical handover, Sniffer, frequency synthesizer, phase-locked loop, PLL, sigma-delta, calibration
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-9486ISBN: 978-91-7415-142-8 (print)OAI: oai:DiVA.org:kth-9485DiVA: diva2:114191
Public defence
2008-11-20, sal D, Forum, KTH, Isafjordsgatan 39, Kista, 14:00 (English)
Opponent
Supervisors
Note
QC 20100706Available from: 2008-11-10 Created: 2008-11-07 Last updated: 2010-07-06Bibliographically approved
List of papers
1. Future 4G front-ends enabling smooth vertical handovers
Open this publication in new window or tab >>Future 4G front-ends enabling smooth vertical handovers
2006 (English)In: IEEE Circuits & Devices, ISSN 8755-3996, E-ISSN 1558-1888, Vol. 22, no 1, 6-15 p.Article in journal (Refereed) Published
Abstract [en]

An overview is given of the most important effects that handover considerations have on the design of multistandard mobile radio transceivers. Focus is on the multitude of design issues and challenges that should be taken into account in the RF/analog front-end part. Topics discussed include the convergence challenge, wireless transceiver design challenge, wireless standards, handover initiation, interworking between GSM and DECT, idle mode issues, possible issues when mobile terminals miss pages, procedure while in active communication in DECT mode, procedure while in active communication in GSM mode, and GSM/WLAN handover.

Keyword
Design; Global system for mobile communications; Local area networks; Mobile telecommunication systems; Radio communication; Standards; Interworking; Mobile radio transceivers; Wireless standards
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-13973 (URN)10.1109/MCD.2006.1598074 (DOI)000235756600003 ()2-s2.0-33644668527 (Scopus ID)
Note
QC 20100706Available from: 2010-07-06 Created: 2010-07-06 Last updated: 2017-12-12Bibliographically approved
2. Optimal Sigma Delta Modulator Architectures for Fractional-N Frequency Synthesis
Open this publication in new window or tab >>Optimal Sigma Delta Modulator Architectures for Fractional-N Frequency Synthesis
Show others...
2010 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 18, no 2, 194-200 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a comparative study of Sigma Delta modulators for use in fractional-N phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.

Keyword
Frequency synthesizers, phase-locked loops (PLLs), phase noise, Sigma Delta modulation
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-13978 (URN)10.1109/TVLSI.2008.2009058 (DOI)000273774700003 ()2-s2.0-75549083172 (Scopus ID)
Funder
Swedish Research Council
Note
QC 20100706. Tidigare titel: Selection of Optimal Sigma Delta Modulator Architecture for Fractional-N Frequency Synthesis.Available from: 2010-07-06 Created: 2010-07-06 Last updated: 2017-12-12Bibliographically approved
3. A CMOS frequency synthesizer for multi-standard wireless devices
Open this publication in new window or tab >>A CMOS frequency synthesizer for multi-standard wireless devices
2003 (English)In: Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems: Vols 1-3 / [ed] Hamdy, N., NEW YORK: IEEE , 2003, 1138-1141 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a CMOS frequency synthesizer for wireless transceivers that support several communication standards namely GSM, WCDMA, IEEE 802.11b, and Bluetooth. The architecture is based on a multi-stage phase-locked loop where each stage differs from the others in the parameters of its charge pump and loop filter. It is designed using mathematical models and refined through simulation using different software tools depending on the required perspective. The architecture and the components presented pave the way to provide a low cost, fully integrated implementation.

Place, publisher, year, edition, pages
NEW YORK: IEEE, 2003
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-13981 (URN)000234964300279 ()0-7803-8294-3 (ISBN)
Conference
46th IEEE International Midwest Symposium on Circuits and Systems, Cairo, EGYPT, DEC 27-30, 2003, Arab Acad Sci & Technol; IEEE Circuits & Syst Soc
Note
QC 20100706Available from: 2010-07-06 Created: 2010-07-06 Last updated: 2010-07-06Bibliographically approved
4. A frequency planning and generation scheme for multi-standard wireless transceivers
Open this publication in new window or tab >>A frequency planning and generation scheme for multi-standard wireless transceivers
2005 (English)In: 12th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2005: Gammarth, 11 December 2005 through 14 December 2005, 2005Conference paper, Published paper (Refereed)
Abstract [en]

This work presents a novel frequency planning scheme associated with a reference frequency generation scheme that has the potential of providing low phase noise contribution for several wireless standards including DCS1800, WCDMA II and III, DECT, WLAN a/b/g and Bluetooth. The scheme is particularly useful when implemented in future technologies and can be extended to cover newer wireless standards in newer bands of interest. It uses a single multi-band voltage-controlled oscillator (VCO) with switching inductors and high speed dividers directly generating the quadrature outputs. The VCO itself covers the frequency ranges from 4.8GHz to 6GHz and from 6.8GHz to 8GHz. Its phase noise is -136dBc/Hz at 1MHz offset from a center frequency of 1.85GHz. The design is sent for fabrication using 0.18ÎŒm CMOS.

Keyword
Cellular telephone systems; Local area networks; Oscillators (electronic); Phase noise; Variable frequency oscillators; Voltage dividers; Wireless local area networks (WLAN), A centers; Frequency ranges; Future technologies; High speeds; Low phase noises; Planning schemes; Quadrature outputs; Reference frequencies; Voltage-controlled oscillators; Wireless standards; Wireless transceivers, Standards
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-13983 (URN)10.1109/ICECS.2005.4633612 (DOI)2-s2.0-56849099704 (Scopus ID)978-997261100-1 (ISBN)
Note
QC 20100706Available from: 2010-07-06 Created: 2010-07-06 Last updated: 2010-07-06Bibliographically approved
5. Vertical handover for 4G multi-standard wireless transceivers
Open this publication in new window or tab >>Vertical handover for 4G multi-standard wireless transceivers
2007 (English)In: 2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS: VOLS 1-4, 2007, 1356-1359 p.Conference paper, Published paper (Refereed)
Abstract [en]

Future best-connected wireless solutions will involve a multitude of network standards between which the user can switch in order to optimize a set of benefits such as cost and performance. As a result of this convergence, the hardware design of the mobile device will require knowledge about the restrictions imposed by the upper networking layers. This paper starts by presenting the requirements for the connection initialization in the WLAN, WiMAX and 3G standards as they pertain to the mobile transceiver design. It is assumed that the mobile device is based on the dual front-end transceiver architecture where the primary transceiver handles the current network connection while the secondary transceiver (Sniffer) searches for an alternative connection. The paper also presents the handover procedures between these standards that will provide, among other things, the timing requirements for the circuit design.

Series
IEEE International Conference on Electronics, Circuits and Systems
Keyword
Computer networks; Integrated circuit manufacture; Local area networks; Mobile devices; Networks (circuits); Object recognition; Portable equipment; Radio systems; Standards; Switching circuits; Telecommunication equipment; Timing circuits; Transceivers; Wireless local area networks (WLAN); Wireless telecommunication systems; Hardware designs; International conferences; Network standards; Wireless transceivers
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-13986 (URN)10.1109/ICECS.2007.4511250 (DOI)000255014801159 ()2-s2.0-50649122512 (Scopus ID)
Conference
14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, MOROCCO, DEC 11-14, 2007
Note
QC 20100706Available from: 2010-07-06 Created: 2010-07-06 Last updated: 2010-07-06Bibliographically approved
6. Wide-Division-Range High-Speed Fully Programmable Frequency Divider
Open this publication in new window or tab >>Wide-Division-Range High-Speed Fully Programmable Frequency Divider
Show others...
2008 (English)In: 2008 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, NEW YORK: IEEE , 2008, 17-20 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the design and implementation of an all-programmable frequency divider with an ultra-wide division range for use in Phase-Locked Loops. The proposed divider uses a fully modular architecture and dynamic logic - implemented in TSMC 0.18 mu m - and can divide input frequencies up to 7.55GHz by any ratio between 8 and 255 while consuming 11mW from a 1.8V power supply. The divider compares very favorably to other implementations reported in literature in terms of division range and frequency of operation.

Place, publisher, year, edition, pages
NEW YORK: IEEE, 2008
Keyword
frequency synthesizers, prescalers, high-speed integrated circuits, DUAL-MODULUS PRESCALER, CMOS TECHNOLOGY
National Category
Engineering and Technology
Identifiers
urn:nbn:se:kth:diva-13990 (URN)10.1109/NEWCAS.2008.4606310 (DOI)000262463700005 ()2-s2.0-52449098048 (Scopus ID)
Conference
Joint IEEE North-East Workshop on Circuits and Systems/TAISA Conference, Montreal, CANADA, JUN 22-25, 2008
Note
QC 20100706Available from: 2010-07-06 Created: 2010-07-06 Last updated: 2010-07-06Bibliographically approved

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Output format
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