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Performance Evaluation and Cache Behavior of LC-Trie for IP-Address Lookup
KTH, School of Electrical Engineering (EES), Communication Networks.
KTH, School of Computer Science and Communication (CSC), Theoretical Computer Science, TCS.
KTH, School of Electrical Engineering (EES), Communication Networks.ORCID iD: 0000-0002-3704-1338
2006 (English)In: Proc. of IEEE 2006 Workshop on High Performance Switching and Routing (HPSR 2006), IEEE , 2006, 29-35 p.Conference paper, Published paper (Refereed)
Abstract [en]

Many IP-address lookup software algorithms use a trie-like data structure to perform longest prefix match. LC-trie is an efficient algorithm that uses level compression and path compression on tries. By using realistic and synthetically generated traces, we study the performance of the LC-trie algorithm. Our study includes trie search depth, prefix vector access behavior, cache behavior, and packet lookup service time. The results show that for a realistic traffic trace, the LC-trie algorithm is capable of performing 20 million packet lookups per second on a Pentium 4, 2.8 GHz computer, which corresponds to a 40 Gb/s link for average sized packets. Further, the results show that LC-trie performs up to five times better on the realistic trace compared to a synthetically generated network trace. This illustrates that the choice of traces may have a large influence on the results when evaluating lookup algorithms.

Place, publisher, year, edition, pages
IEEE , 2006. 29-35 p.
National Category
Telecommunications
Identifiers
URN: urn:nbn:se:kth:diva-6670DOI: 10.1109/HPSR.2006.1709677ISI: 000239877600005Scopus ID: 2-s2.0-41549151304ISBN: 0780395697 (print)ISBN: 978-078039569-5 OAI: oai:DiVA.org:kth-6670DiVA: diva2:11444
Conference
2006 Workshop on High Performance Switching and Routing, HPSR 2006; Poznan; Poland; 7-9 June 2006
Note

QC 20141117

Available from: 2006-12-19 Created: 2006-12-19 Last updated: 2014-11-17Bibliographically approved
In thesis
1. Design and evaluation of network processor systems and forwarding applications
Open this publication in new window or tab >>Design and evaluation of network processor systems and forwarding applications
2006 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

During recent years, both the Internet traffic and packet transmission rates have been growing rapidly, and new Internet services such as VPNs, QoS and IPTV have emerged. To meet increasing line speed requirements and to support current and future Internet services, improvements and changes are needed in current routers both with respect to hardware architectures and forwarding applications. High speed routers are nowadays mainly based on application specific integrated circuits (ASICs), which are custom made and not flexible enough to support diverse services. Generalpurpose processors offer flexibility, but have difficulties to in handling high data rates. A number of software IP-address lookup algorithms have therefore been developed to enable fast packet processing in general-purpose processors. Network processors have recently emerged to provide the performance of ASICs combined with the programmability of general-purpose processors.

This thesis provides an evaluation of router design including both hardware architectures and software applications. The first part of the thesis contains an evaluation of various network processor system designs. We introduce a model for network processor systems which is used as a basis for a simulation tool. Thereafter, we study two ways to organize processing elements (PEs) inside a network processor to achieve parallelism: a pipelined and a pooled organization. The impact of using multiple threads inside a single PE is also studied. In addition, we study the queueing behavior and packet delays in such systems. The results show that parallelism is crucial to achieving high performance,but both the pipelined and the pooled processing-element topologies achieve comparable performances. The detailed queueing behavior and packet delay results have been used to dimension queues, which can be used as guidelines for designing memory subsystems and queueing disciplines.

The second part of the thesis contains a performance evaluation of an IP-address lookup algorithm, the LC-trie. The study considers trie search depth, prefix vector access behavior, cache behavior, and packet lookup service time. For the packet lookup service time, the evaluation contains both experimental results and results obtained from a model. The results show that the LC-trie is an efficient route lookup algorithm for general-purpose processors, capable of performing 20 million packet lookups per second on a Pentium 4, 2.8 GHz computer, which corresponds to a 40 Gb/s link for average sized packets. Furthermore, the results show the importance of choosing packet traces when evaluating IP-address lookup algorithms: real-world and synthetically generated traces may have very different behaviors.

The results presented in the thesis are obtained through studies of both hardware architectures and software applications. They could be used to guide the design of next-generation routers.

Place, publisher, year, edition, pages
Stockholm: KTH, 2006. vii, 15 p.
Series
Trita-EE, ISSN 1653-5146 ; 2006:054
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-4248 (URN)
Presentation
2006-12-19, Q2, KTH, Osquldas väg 10, Stockholm, 14:00
Opponent
Supervisors
Note
QC 20101112Available from: 2006-12-19 Created: 2006-12-19 Last updated: 2010-11-12Bibliographically approved

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Karlsson, Gunnar

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