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Design and evaluation of network processor systems and forwarding applications
KTH, School of Electrical Engineering (EES).
2006 (English)Licentiate thesis, comprehensive summary (Other scientific)
Abstract [en]

During recent years, both the Internet traffic and packet transmission rates have been growing rapidly, and new Internet services such as VPNs, QoS and IPTV have emerged. To meet increasing line speed requirements and to support current and future Internet services, improvements and changes are needed in current routers both with respect to hardware architectures and forwarding applications. High speed routers are nowadays mainly based on application specific integrated circuits (ASICs), which are custom made and not flexible enough to support diverse services. Generalpurpose processors offer flexibility, but have difficulties to in handling high data rates. A number of software IP-address lookup algorithms have therefore been developed to enable fast packet processing in general-purpose processors. Network processors have recently emerged to provide the performance of ASICs combined with the programmability of general-purpose processors.

This thesis provides an evaluation of router design including both hardware architectures and software applications. The first part of the thesis contains an evaluation of various network processor system designs. We introduce a model for network processor systems which is used as a basis for a simulation tool. Thereafter, we study two ways to organize processing elements (PEs) inside a network processor to achieve parallelism: a pipelined and a pooled organization. The impact of using multiple threads inside a single PE is also studied. In addition, we study the queueing behavior and packet delays in such systems. The results show that parallelism is crucial to achieving high performance,but both the pipelined and the pooled processing-element topologies achieve comparable performances. The detailed queueing behavior and packet delay results have been used to dimension queues, which can be used as guidelines for designing memory subsystems and queueing disciplines.

The second part of the thesis contains a performance evaluation of an IP-address lookup algorithm, the LC-trie. The study considers trie search depth, prefix vector access behavior, cache behavior, and packet lookup service time. For the packet lookup service time, the evaluation contains both experimental results and results obtained from a model. The results show that the LC-trie is an efficient route lookup algorithm for general-purpose processors, capable of performing 20 million packet lookups per second on a Pentium 4, 2.8 GHz computer, which corresponds to a 40 Gb/s link for average sized packets. Furthermore, the results show the importance of choosing packet traces when evaluating IP-address lookup algorithms: real-world and synthetically generated traces may have very different behaviors.

The results presented in the thesis are obtained through studies of both hardware architectures and software applications. They could be used to guide the design of next-generation routers.

Place, publisher, year, edition, pages
Stockholm: KTH , 2006. , vii, 15 p.
Series
Trita-EE, ISSN 1653-5146 ; 2006:054
National Category
Telecommunications
Identifiers
URN: urn:nbn:se:kth:diva-4248OAI: oai:DiVA.org:kth-4248DiVA: diva2:11446
Presentation
2006-12-19, Q2, KTH, Osquldas väg 10, Stockholm, 14:00
Opponent
Supervisors
Note
QC 20101112Available from: 2006-12-19 Created: 2006-12-19 Last updated: 2010-11-12Bibliographically approved
List of papers
1. Designing and Evaluating Network Processor Applications
Open this publication in new window or tab >>Designing and Evaluating Network Processor Applications
2005 (English)In: IEEE Workshop on High Performance Switching and Routing: Hong Kong, PEOPLES R CHINA, MAY 12-14, 2005, 2005, 142-146 p.Conference paper, Published paper (Refereed)
Abstract [en]

Network processors try to achieve the performance of traditional ASICs while providing programmability of general-purpose processors. In short, a network processor provides a programming interface for implementing packet forwarding services. It is therefore important to study how efficient different designs are, as well as investigate how difficult they are to program. In this paper, a network processor model is introduced which is used as a basis for a simulation tool. By sending packets into the simulator, throughput, latency, and utilization can be measured. An IPv4 forwarding application is evaluated using two different processing element topologies: a pipelined and a pooled. In addition, the performance impact of using multiple threads inside a single processing element is evaluated. The results show that the use of parallelism is crucial to achieve high performance, but that both the pipelined topology and pooled topology achieve comparable performance.

Keyword
network processors; parallel processing; pipeline processing; performance evaluation
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-9329 (URN)10.1109/HPSR.2005.1503211 (DOI)000231187500029 ()2-s2.0-27644566537 (Scopus ID)
Note
QC 20100726Available from: 2008-10-30 Created: 2008-10-20 Last updated: 2013-06-12Bibliographically approved
2. Performance Evaluation and Cache Behavior of LC-Trie for IP-Address Lookup
Open this publication in new window or tab >>Performance Evaluation and Cache Behavior of LC-Trie for IP-Address Lookup
2006 (English)In: Proc. of IEEE 2006 Workshop on High Performance Switching and Routing (HPSR 2006), IEEE , 2006, 29-35 p.Conference paper, Published paper (Refereed)
Abstract [en]

Many IP-address lookup software algorithms use a trie-like data structure to perform longest prefix match. LC-trie is an efficient algorithm that uses level compression and path compression on tries. By using realistic and synthetically generated traces, we study the performance of the LC-trie algorithm. Our study includes trie search depth, prefix vector access behavior, cache behavior, and packet lookup service time. The results show that for a realistic traffic trace, the LC-trie algorithm is capable of performing 20 million packet lookups per second on a Pentium 4, 2.8 GHz computer, which corresponds to a 40 Gb/s link for average sized packets. Further, the results show that LC-trie performs up to five times better on the realistic trace compared to a synthetically generated network trace. This illustrates that the choice of traces may have a large influence on the results when evaluating lookup algorithms.

Place, publisher, year, edition, pages
IEEE, 2006
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-6670 (URN)10.1109/HPSR.2006.1709677 (DOI)000239877600005 ()2-s2.0-41549151304 (Scopus ID)0780395697 (ISBN)978-078039569-5 (ISBN)
Conference
2006 Workshop on High Performance Switching and Routing, HPSR 2006; Poznan; Poland; 7-9 June 2006
Note

QC 20141117

Available from: 2006-12-19 Created: 2006-12-19 Last updated: 2014-11-17Bibliographically approved
3. Queueing Behavior and Packet Delays in Network Processor Systems
Open this publication in new window or tab >>Queueing Behavior and Packet Delays in Network Processor Systems
2007 (English)In: 15th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems: Bogazici Univ, Dept Comp Engn, Istanbul, TURKEY, OCT 24-26, 2007 / [ed] Caglayan M. U.; Field AJ; Gelenbe E., 2007, 217-224 p.Conference paper, Published paper (Refereed)
Abstract [en]

Network processor systems provide the performance of ASICs combined withthe programmability of general-purpose processors. One of the main challengesin designing these systems is the memory subsystem used when forwarding andqueueing packets. In this work, we study the queueing behavior and packet delaysin a network processor system which works as a router. We introduce a systemmodel and a simulation tool based on the model. Using the simulation tool, bothbest-effort and diffserv IPv4 forwarding were modeled and tested using real-worldand synthetically generated packet traces. The results on queueing behavior havebeen used to dimension various queues, and can be used as guidelines for designingmemory subsystems and queueing disciplines. In particular, a system withsmall queue sizes has been proposed. The results on packet delays also show thatour diffserv setup provides good service differentiation for best-effort and prioritypackets. Finally, the study reveals that the choice of traces has a large impact onthe results when evaluating router and switch architectures.

Series
International Symposium on Modeling Analysis and Simulation of Computer and Telecommunication Systems Proceedings, ISSN 1526-7539
Keyword
network processor; router; queueing behavior
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-9330 (URN)10.1109/MASCOTS.2007.56 (DOI)000265212400031 ()2-s2.0-57849125895 (Scopus ID)978-1-4244-1853-4 (ISBN)
Note
QC 20100726Available from: 2008-10-20 Created: 2008-10-20 Last updated: 2013-09-09Bibliographically approved

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